libs/libc/risc-v: Refresh memcpy and memset with XLEN-adaptive loops. - #19781
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xiaoxiang781216 merged 1 commit intoAug 12, 2026
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Rewrite arch_memcpy.S and arch_memset.S to be register-width aware on both RV32 and RV64 using REG_L/REG_S/SZREG macros from asm.h. memcpy gains: - 16xSZREG unrolled main loop (128B/iter on RV64, 64B on RV32). - Shift-merge path for misaligned src: reads two aligned words straddling each output word and shifts them together, so no load or store is ever misaligned. - Single SZREG and byte loops for remainder and small copies. memset gains: - 32xSZREG unrolled main loop (256B/iter on RV64, 128B on RV32) using Duff's device for non-power-of-two remainders. - .option norvc ensures fixed 4-byte instruction width for correct jump offset calculation in the Duff's device entry. - Zero-length input handled correctly (branch to guarded tail). The old memcpy always used lw/sw even on RV64, wasting half the memory bandwidth. The old memset unrolled only 16 bytes per iteration. Signed-off-by: ganjing <ganjing@xiaomi.com>
xiaoxiang781216
approved these changes
Aug 11, 2026
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@Fishwaldo could you benchmark this patch on your hardware? |
simbit18
approved these changes
Aug 11, 2026
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libs/libc/risc-v: Refresh memcpy and memset with XLEN-adaptive loops.
Summary
Rewrite arch_memcpy.S and arch_memset.S to be register-width aware on
both RV32 and RV64 using REG_L/REG_S/SZREG macros from asm.h.
The old memcpy always used lw/sw even on RV64, wasting half the memory
bandwidth, and unrolled only 64 bytes per iteration. The old memset
unrolled only 16 bytes per iteration.
Changes:
shift-merge path for misaligned source so no load or store is ever
unaligned, single SZREG and byte loops for remainder.
with Duff's device for non-power-of-two remainders. .option norvc
ensures fixed 4-byte instruction width for correct jump calculation.
Zero-length input handled correctly.
Impact
Testing
I confirm that changes are verified on local setup and works as intended:
Correctness: arch_libctest reports PASSED for memcpy and memset across
alignments 0-7 and sizes 1-128.
Performance (QEMU RV32, rdcycle, 128 bytes, 100 iterations average):
Testing logs (optimized):