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Signed-off-by: Saif <saifuddin.kaijar@amd.com>
Move the resource solver implementation from device-specific aie2_solver to a generic amdxdna_solver that can be shared across different hardware generations. This refactoring enables better code reuse and maintenance. Key changes: - Rename aie2_solver.[ch] to amdxdna_solver.[ch] to reflect the generic nature of the resource solver implementation - Update includes in aie2_ctx.c and aie2_pci.c to use the new header - Add amdxdna_aux_drv.c to support auxiliary bus based driver binding, enabling use on embedded ARM platforms - Modify Makefile and Kbuild to support both PCI and AUX bus types - Change XDNA_BUS_TYPE from hardcoded to configurable via environment - Replace OF (device tree) bus type with AUX bus type for better platform device support The solver now provides a unified interface for resource allocation and management across both x86_64 PCI-based and ARM64 auxiliary bus-based deployments. Signed-off-by: Claude Opus 4.6 <noreply@anthropic.com>
Extract common DRM and device management code from PCI-specific driver into new amdxdna_drv.c/h files. This enables code sharing between PCI and auxiliary bus driver variants. The refactoring moves the following to common code: - DRM driver operations (open, close, file_ops) - IOCTL handlers (get_info, set_state, get_array) - Device initialization and cleanup (amdxdna_dev_init/cleanup) - Client management (amdxdna_client_cleanup) - Common data structures and definitions PCI driver retains: - Hardware-specific probe/remove functions - PCI device table and identification - IOMMU initialization (PCI-specific) - SR-IOV configuration - Power management operations Changes: - Add amdxdna_drv.c with common DRM/device functions - Add amdxdna_drv.h with shared structures and ops definitions - Simplify amdxdna_pci_drv.c to use common init/cleanup functions - Reduce amdxdna_pci_drv.h to PCI-specific definitions only - Update amdxdna_aux_drv.c to use common module definitions - Move struct amdxdna_dev_info to PCI header (hardware-specific) - Add amdxdna_for_each_client macro to common header - Update Kbuild to include amdxdna_drv.o This refactoring eliminates ~460 lines of duplicate code while maintaining full compatibility with existing PCI driver functionality. Signed-off-by: Claude Opus 4.6 <noreply@anthropic.com>
Add comprehensive hardware context (hwctx) management helpers for common infrastructure shared across different hardware implementations (AIE2, AIE4). **Resource allocation helpers (amdxdna_solver.c)**: - amdxdna_alloc_resource(): Allocates AIE resources based on hwctx QoS requirements and column configuration - amdxdna_release_resource(): Releases previously allocated AIE resources **Column list management (amdxdna_ctx.c)**: - amdxdna_hwctx_col_list(): Calculates and allocates column list for hwctx based on number of tiles and alignment requirements **Private data lifecycle (amdxdna_ctx.c)**: - amdxdna_hwctx_priv_init(): Initializes hwctx private data including DRM GPU scheduler setup, scheduler entity creation, command buffer allocation, and semaphore/mutex initialization - amdxdna_hwctx_priv_fini(): Cleanup for hwctx private data - DRM scheduler cleanup, command buffer release, mutex destruction, column list freeing **Complete hwctx finalization (amdxdna_ctx.c)**: - amdxdna_hwctx_fini(): Complete hwctx cleanup that stops DRM scheduler, calls release_resource callback, restarts scheduler to drain pending jobs, waits for all jobs to complete, and destroys sync objects **Sync object management (amdxdna_ctx.c)**: - amdxdna_ctx_syncobj_create(): Creates DRM sync object for hwctx - amdxdna_ctx_syncobj_destroy(): Destroys DRM sync object **Struct reorganization**: - Moved struct amdxdna_hwctx_priv from aie2_pci.h to amdxdna_ctx.h to enable common code access to private hwctx data - Added constants: HWCTX_MAX_TIMEOUT, MAX_CHAIN_CMDBUF_SIZE These functions provide common infrastructure for hwctx management, reducing code duplication across different hardware implementations and improving modularity. Note: ARM64 builds may fail if the kernel doesn't export DRM scheduler symbols. This is a kernel configuration issue - the code is correct for kernels that properly export these symbols (like x86_64 upstream kernels). Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Implement auxiliary bus driver for ARM64 AUX devices and add VE2 hardware placeholder following the AIE2 PCI driver pattern. Auxiliary Driver (amdxdna_aux_drv.c): - Probe function with DRM device allocation via devm_drm_dev_alloc() - Uses framework's amdxdna_dev_init()/amdxdna_dev_cleanup() - DMA mask configuration for auxiliary devices (64-bit with 32-bit fallback) - Device matching for "xilinx_aie.amdxdna" - Proper error handling with cleanup paths VE2 Hardware Support (ve2_aux.c/h): - Placeholder implementation matching amdxdna_dev_ops interface - All operations return -EOPNOTSUPP until full implementation - Functions: init, fini, hwctx management, cmd_submit, get_aie_info, etc. - Ready for real VE2 hardware implementation Move AIE-specific code to PCI driver: - Move notifier_wq and notifier_lock initialization from common amdxdna_dev_init() to PCI-specific amdxdna_probe() - Move LOCKDEP validation for notifier_lock to PCI driver - Move workqueue cleanup from amdxdna_dev_cleanup() to PCI remove - AUX driver doesn't need AIE-specific notifier infrastructure Build configuration: - Added ve2_aux.o to AUX build in Kbuild - VE2 device info structure using ve2_ops The auxiliary driver follows the same pattern as the PCI driver but adapted for auxiliary bus devices. VE2 support is added as a placeholder similar to how AIE2 support is structured for PCI devices. Signed-off-by: Saifuddin Kaijar <saifuddin.kaijar@amd.com> Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Separate the cmd_submit and cmd_wait paths cleanly across the
amdxdna common framework and the AIE2/VE2 backend drivers.
The previous refactoring (patch 0003) moved hardware context lifecycle
into the common layer and introduced amdxdna_cmd_submit() as a
framework helper. However, the cmd_wait path was left incomplete:
- amdxdna_cmd_wait() was declared in amdxdna_ctx.h but never
implemented in amdxdna_ctx.c.
- The WAIT_CMD ioctl was missing from amdxdna_drm_ioctls[] and
from the upstream UAPI enum.
- cmd_wait was absent from struct amdxdna_dev_ops, so no backend
could provide a hardware-specific wait implementation.
- The aie2_cmd_wait() helper in aie2_ctx.c was file-scoped (static)
and not wired into the ops vtable.
This patch completes the cmd_submit/cmd_wait re-architecture:
1. UAPI (include/uapi/drm/amdxdna_accel.h):
- Add DRM_AMDXDNA_WAIT_CMD = 9 to the ioctl enum.
- Add struct amdxdna_drm_wait_cmd with hwctx, timeout, seq fields.
- Add DRM_IOCTL_AMDXDNA_WAIT_CMD macro.
- Keep DRM_AMDXDNA_GET_ARRAY = 10 explicit to preserve numbering.
2. amdxdna_drv.h:
- Add cmd_wait() callback to struct amdxdna_dev_ops:
int (*cmd_wait)(struct amdxdna_hwctx *hwctx, u64 seq,
u32 timeout_ms);
Backends that do not support waiting return -EOPNOTSUPP.
3. amdxdna_ctx.c (common framework):
- Implement amdxdna_cmd_wait(): looks up the hwctx under SRCU
read lock and dispatches to ops->cmd_wait().
- Implement amdxdna_drm_wait_cmd_ioctl(): validates args and
calls amdxdna_cmd_wait().
4. amdxdna_drv.c:
- Register the WAIT_CMD ioctl:
DRM_IOCTL_DEF_DRV(AMDXDNA_WAIT_CMD,
amdxdna_drm_wait_cmd_ioctl, 0)
5. aie2_ctx.c:
- Rename the static aie2_cmd_wait() to aie2_cmd_wait_op() and
change its signature to match ops->cmd_wait:
int aie2_cmd_wait_op(struct amdxdna_hwctx *hwctx, u64 seq,
u32 timeout_ms);
The function waits on the syncobj fence with a timeout derived
from timeout_ms (0 = MAX_SCHEDULE_TIMEOUT).
- Wire it into aie2_pci_ops.cmd_wait.
- Update callers within aie2_ctx.c (hwctx_cfg_debug_bo,
hwctx_sync_debug_bo) to use the new function directly.
6. ve2_aux.c:
- Add a stub ve2_cmd_wait() returning -EOPNOTSUPP.
- Wire it into ve2_ops.cmd_wait.
Design rationale:
- cmd_submit (framework → ops layer): The common amdxdna_cmd_submit()
handles job allocation, BO pinning, fence creation, and SRCU
locking. The backend ops->cmd_submit() handles scheduler job
initialization, BO reservation, and drm_sched_entity_push_job().
This boundary is correct and unchanged.
- cmd_wait (framework → ops layer): The common amdxdna_cmd_wait()
handles hwctx lookup and SRCU locking. The backend ops->cmd_wait()
handles fence retrieval and blocking wait. This matches the
established pattern and is now consistent for all backends.
- The WAIT_CMD ioctl must exist in the common layer (amdxdna_drv.c)
because it is a hardware-agnostic scheduling primitive — the
scheduler (drm_gpu_scheduler + syncobj) is set up in the common
amdxdna_hwctx_priv_init(), and the fence timeline is managed by
drm_syncobj, which is backend-independent.
Fixes: Missing WAIT_CMD ioctl registration after framework split.
Signed-off-by: Saifuddin Kaijar <saifuddin.kaijar@amd.com>
Co-Authored-By: Claude Sonnet 4 <noreply@anthropic.com>
Add minimal fixes to handle kernel API variations: 1. Add missing function prototypes for amdxdna_dma_map_bo() and amdxdna_dma_unmap_bo() to amdxdna_drv.h (these were present in the original amdxdna_pci_drv.h). 2. Add HAVE_6_10_drm_sched_start_full_recovery case for drm_sched_start() to handle kernel 6.10+ which requires a second boolean argument. This matches the original version checking pattern in aie2_ctx.c. These changes align with the existing kernel version compatibility infrastructure and maintain compatibility across different kernel versions. Signed-off-by: Saifuddin Kaijar <saifuddin.kaijar@amd.com> Co-Authored-By: Claude Sonnet 4 <noreply@anthropic.com>
The FOP_UNSIGNED_OFFSET flag is not available in all kernel versions. Add an ifdef guard to maintain compatibility, matching the pattern used in the original amdxdna_pci_drv.c. This fixes the build error on kernels where FOP_UNSIGNED_OFFSET is not defined. Signed-off-by: Saifuddin Kaijar <saifuddin.kaijar@amd.com> Co-Authored-By: Claude Sonnet 4 <noreply@anthropic.com>
Restore the amdxdna_sva_init() and amdxdna_sva_fini() helper functions that were present in the original amdxdna_pci_drv.c. The patches had inlined this code, but the original version had proper error handling and importantly included the conditional check: if (!amdxdna_iova_on(xdna)) This check is critical because SVA (Shared Virtual Addressing) should only be initialized when IOVA is not being used. Without this check, systems with IOMMU domains would incorrectly attempt SVA initialization. Changes: - Add back amdxdna_sva_init() helper with proper error handling - Add back amdxdna_sva_fini() helper with NULL check - Update amdxdna_drm_open() to conditionally call sva_init only when IOVA is not enabled, matching the original behavior - Update amdxdna_client_cleanup() to use amdxdna_sva_fini() - Fix duplicate mutex_destroy() call This aligns the code with the original implementation in amdxdna_pci_drv.c and ensures correct behavior on systems with both IOMMU and non-IOMMU configurations. Signed-off-by: Saifuddin Kaijar <saifuddin.kaijar@amd.com> Co-Authored-By: Claude Sonnet 4 <noreply@anthropic.com>
…eanup
Add the missing pieces from the original amdxdna_pci_drv.c:
1. Initialize dev_heap_chunks list head in amdxdna_drm_open():
- INIT_LIST_HEAD(&client->dev_heap_chunks)
- This is required for expandable device heap support
2. Properly cleanup dev_heap_chunks in amdxdna_client_cleanup():
- Replace simple dev_heap cleanup with while loop that iterates
through all chunks in the dev_heap_chunks list
- Each chunk needs its reference dropped properly
- This matches the original implementation
3. Remove unused 'int ret' variable from amdxdna_drm_open()
These changes ensure proper memory management for expandable device
heaps, matching the original behavior in amdxdna_pci_drv.c.
Signed-off-by: Saifuddin Kaijar <saifuddin.kaijar@amd.com>
Co-Authored-By: Claude Sonnet 4 <noreply@anthropic.com>
Add the amdxdna_show_fdinfo() function that was present in the original amdxdna_pci_drv.c but missing from the refactored amdxdna_drv.c. This function provides per-file descriptor information about memory usage through the DRM fdinfo interface, which is critical for debugging and monitoring memory allocation across different clients. The function reports: - amdxdna-heap-alloc: Device heap memory usage - amdxdna-internal-alloc: Internal buffer object usage - amdxdna-external-alloc: External/imported buffer object usage - DRM standard memory stats via drm_show_memory_stats() Also register the function in the drm_driver structure via the .show_fdinfo callback. This enables tools like 'cat /proc/<pid>/fdinfo/<fd>' to show detailed memory usage statistics for XDNA accelerator file descriptors. Signed-off-by: Saifuddin Kaijar <saifuddin.kaijar@amd.com> Co-Authored-By: Claude Sonnet 4 <noreply@anthropic.com>
Critical fixes found from comprehensive comparison with original:
1. Add module init/exit functions with carveout support:
- Replace module_pci_driver() macro with explicit
amdxdna_mod_init() and amdxdna_mod_exit()
- Call amdxdna_carveout_init() on module load
- Call amdxdna_carveout_fini() on module unload
- This is essential for systems without IOMMU that use
carveout memory allocation
2. Add .show_fdinfo to file_operations structure:
- Original had .show_fdinfo = drm_show_fdinfo in fops
- This is separate from the drm_driver's show_fdinfo callback
- Enables standard DRM fdinfo reporting via /proc
The carveout init/fini calls were being skipped when using the
module_pci_driver() convenience macro, which would cause memory
allocation failures on non-IOMMU systems.
Signed-off-by: Saifuddin Kaijar <saifuddin.kaijar@amd.com>
Co-Authored-By: Claude Sonnet 4 <noreply@anthropic.com>
Restore critical missing functions from original aie2_ctx.c that handle expandable device heap support: 1. aie2_hwctx_map_heap(): - Maps all heap chunks to firmware - Handles pinning and reference counting - Uses dev_heap_chunks list for expandable heaps - Critical for firmware to access device memory 2. aie2_hwctx_release_heap(): - Releases all pinned heap chunks - Unpins and drops references for each chunk - Properly tracks last_pinned_chunk 3. Update aie2_hwctx_init(): - Remove old single-heap (dev_heap) pin/unpin code - Use aie2_hwctx_map_heap() instead of direct map_host_buf - Add DPM level calculation and request - Proper error path with release_dpm label - Calculate max_opc based on column configuration 4. Update aie2_hwctx_fini(): - Replace amdxdna_hwctx_fini() with explicit sequence - Add DPM level release - Use aie2_hwctx_release_heap() instead of single heap unpin - Properly handle scheduler stop/start and entity destroy - Remove single heap references (priv->heap) 5. Update aie2_hwctx_restart(): - Use aie2_hwctx_map_heap() for expandable heap support These changes align with the expandable device heap architecture where client->dev_heap_chunks contains a list of memory chunks that can grow dynamically, replacing the old single dev_heap approach. Signed-off-by: Saifuddin Kaijar <saifuddin.kaijar@amd.com> Co-Authored-By: Claude Sonnet 4 <noreply@anthropic.com>
Signed-off-by: Saif <saifuddin.kaijar@amd.com>
Signed-off-by: Saif <saifuddin.kaijar@amd.com>
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Pull request overview
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This PR appears to upstream/restructure the AMD XDNA driver by removing a large out-of-tree driver build and moving/expanding the in-kernel drivers/accel/amdxdna implementation, including new IOCTLs and heap/DPM/resource-management changes.
Changes:
- Remove legacy/out-of-tree driver sources and build integration under
src/driver/amdxdnaand related CMake/DKMS files. - Add VE2 auxiliary-bus scaffolding and refactor common driver definitions into
amdxdna_drv.[ch]. - Extend the UAPI and driver functionality (e.g.,
WAIT_CMDIOCTL, heap chunk expansion, DPM reference counting, solver helpers).
Reviewed changes
Copilot reviewed 56 out of 133 changed files in this pull request and generated 5 comments.
Show a summary per file
| File | Description |
|---|---|
| src/driver/amdxdna/aie4_message.h | Removed legacy out-of-tree AIE4 messaging header. |
| src/driver/amdxdna/aie4_host_queue.h | Removed legacy host-queue definitions for out-of-tree driver. |
| src/driver/amdxdna/aie4_error.c | Removed legacy out-of-tree AIE4 async error handling implementation. |
| src/driver/amdxdna/aie4_dpt.c | Removed legacy out-of-tree firmware log/trace parsing. |
| src/driver/amdxdna/aie4_devel.h | Removed legacy out-of-tree development/test header. |
| src/driver/amdxdna/aie4_devel.c | Removed legacy out-of-tree UMQ hello test code. |
| src/driver/amdxdna/aie2_tdr.h | Removed legacy out-of-tree TDR header. |
| src/driver/amdxdna/aie2_tdr.c | Removed legacy out-of-tree TDR implementation. |
| src/driver/amdxdna/aie2_smu.c | Removed legacy out-of-tree SMU implementation. |
| src/driver/amdxdna/aie2_psp.c | Removed legacy out-of-tree PSP implementation. |
| src/driver/amdxdna/aie2_pm.c | Removed legacy out-of-tree power management implementation. |
| src/driver/amdxdna/aie2_pci.h | Removed legacy out-of-tree AIE2 PCI header. |
| src/driver/amdxdna/aie2_msg_priv.h | Removed legacy out-of-tree firmware message definitions. |
| src/driver/amdxdna/aie2_hwctx.c | Removed legacy out-of-tree hardware context management. |
| src/driver/amdxdna/aie2_error.c | Removed legacy out-of-tree async error handling for AIE2. |
| src/driver/amdxdna/aie2_dpt.c | Removed legacy out-of-tree DPT (FW log/trace) implementation. |
| src/driver/amdxdna/Makefile | Removed legacy out-of-tree driver Makefile. |
| src/driver/amdxdna/Kbuild | Removed legacy out-of-tree driver Kbuild. |
| src/driver/CMakeLists.txt | Removed legacy CMake driver build logic. |
| src/driver/CMake/config/dkms.conf.in | Removed legacy DKMS config template. |
| src/CMakeLists.txt | Stopped building the legacy driver subdirectory from this CMake tree. |
| include/uapi/drm/amdxdna_accel.h | Added WAIT_CMD IOCTL ID and struct and exported ioctl macro. |
| drivers/accel/amdxdna/ve2_aux.h | Added VE2 auxiliary-bus header and ops declaration. |
| drivers/accel/amdxdna/ve2_aux.c | Added stub VE2 ops returning -EOPNOTSUPP. |
| drivers/accel/amdxdna/npu6_regs.c | Added col_opc and dev_heap_max_size for NPU6. |
| drivers/accel/amdxdna/npu5_regs.c | Added col_opc and dev_heap_max_size for NPU5. |
| drivers/accel/amdxdna/npu4_regs.c | Added ADD_HOST_BUFFER feature flag, col_opc, and dev_heap_max_size for NPU4. |
| drivers/accel/amdxdna/npu1_regs.c | Added col_opc and dev_heap_max_size for NPU1. |
| drivers/accel/amdxdna/amdxdna_solver.h | Renamed solver header guard, added GOPS helper and hwctx resource helpers. |
| drivers/accel/amdxdna/amdxdna_solver.c | Implemented xrs_get_gops() and factored hwctx resource alloc/release wrappers. |
| drivers/accel/amdxdna/amdxdna_pci_drv.h | Moved common driver structs/macros into amdxdna_drv.h and added heap max size to dev_info. |
| drivers/accel/amdxdna/amdxdna_pci_drv.c | Refactored probe/remove to use common init/cleanup, and moved module metadata to macros. |
| drivers/accel/amdxdna/amdxdna_gem.h | Added heap-chunk list hook in GEM object and minor signature formatting updates. |
| drivers/accel/amdxdna/amdxdna_gem.c | Implemented heap chunk tracking, deterministic heap UVA logic, heap growth handling (-EAGAIN), and DEV BO clflush across chunks. |
| drivers/accel/amdxdna/amdxdna_drv.h | Added new common driver header consolidating core structs, ops, and driver metadata. |
| drivers/accel/amdxdna/amdxdna_drv.c | Added common DRM open/close/ioctl table and common device init/cleanup helpers. |
| drivers/accel/amdxdna/amdxdna_ctx.h | Added hwctx private state definition, wait ioctl prototype, and shared hwctx helper APIs. |
| drivers/accel/amdxdna/amdxdna_ctx.c | Added WAIT_CMD ioctl implementation, hwctx common helpers, syncobj helper refactor, and scheduler init refactor. |
| drivers/accel/amdxdna/amdxdna_aux_drv.c | Added auxiliary-bus probe/remove path for VE2. |
| drivers/accel/amdxdna/aie2_pm.c | Added DPM refcounting, GOPS-based DPM calculation, resume helper, and more power modes. |
| drivers/accel/amdxdna/aie2_pci.h | Added heap max size constant, DPM refcnt array, col_opc, and new feature/op prototypes. |
| drivers/accel/amdxdna/aie2_pci.c | Switched to common solver header, restored PM state on resume, bounded DPM table size, and set sys-eff factor default. |
| drivers/accel/amdxdna/aie2_msg_priv.h | Added MSG_OP_ADD_HOST_BUFFER opcode. |
| drivers/accel/amdxdna/aie2_message.c | Added chunked host-buffer mapping (MAP_HOST_BUFFER + ADD_HOST_BUFFER). |
| drivers/accel/amdxdna/aie2_ctx.c | Added heap chunk pin/notify logic, moved common col-list logic, added DPM request/release per hwctx, and implemented heap expansion callback. |
| drivers/accel/amdxdna/Makefile | Added AUX build option and made XDNA_BUS_TYPE configurable. |
| drivers/accel/amdxdna/Kbuild | Added new objects (drv/solver/aux) and integrated PCI/AUX build targets. |
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| #else | ||
| ret = drm_sched_init(sched, sched_ops, NULL, DRM_SCHED_PRIORITY_COUNT, | ||
| HWCTX_MAX_CMDS, 0, | ||
| timeout_ms ? timeout_ms : MAX_SCHEDULE_TIMEOUT, |
There was a problem hiding this comment.
On the non-HAVE_6_15_drm_sched_init path, timeout_ms is passed directly to drm_sched_init(). That older API expects a timeout in jiffies (drivers typically pass msecs_to_jiffies(...)), so this will scale timeouts incorrectly (e.g., 1000ms becomes 1000 jiffies). Convert timeout_ms to jiffies (and keep MAX_SCHEDULE_TIMEOUT as the no-timeout sentinel) to preserve behavior across kernel versions.
Suggested change
| timeout_ms ? timeout_ms : MAX_SCHEDULE_TIMEOUT, | |
| timeout_ms ? msecs_to_jiffies(timeout_ms) : MAX_SCHEDULE_TIMEOUT, |
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| if (abo->type == AMDXDNA_BO_DEV_HEAP && | ||
| abo->mem.uva == AMDXDNA_INVALID_ADDR && abo->client) | ||
| return amdxdna_dev_heap_uva(abo); |
There was a problem hiding this comment.
amdxdna_dev_heap_uva() walks client->dev_heap_chunks to compute an offset, but amdxdna_gem_uva() calls it without taking client->mm_lock. Since heap chunks can be appended concurrently (heap expansion), this risks list corruption/UAF or returning inconsistent UVAs. Consider taking client->mm_lock around the computation (or caching the chunk offset/UVA at chunk creation time so gem_uva() does not need to traverse the list).
| return ndev->max_dpm_level; | ||
|
|
||
| for (level = 0; level <= ndev->max_dpm_level; level++) { | ||
| if (req_gops <= opc * ndev->priv->dpm_clk_tbl[level].hclk / 1000) |
There was a problem hiding this comment.
The expression opc * ...hclk is computed in 32-bit arithmetic (opc and hclk are u32), which can overflow and cause an incorrect DPM level selection. Use u64 for the multiplication/division (e.g., cast opc or hclk to u64) and compare against req_gops safely.
Suggested change
| if (req_gops <= opc * ndev->priv->dpm_clk_tbl[level].hclk / 1000) | |
| if ((u64)req_gops <= (u64)opc * ndev->priv->dpm_clk_tbl[level].hclk / 1000) |
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| */ | ||
| #define AMDXDNA_DRIVER_MAJOR 0 | ||
| #define AMDXDNA_DRIVER_MINOR 6 |
There was a problem hiding this comment.
This PR adds a new exported UAPI IOCTL (DRM_AMDXDNA_WAIT_CMD), but the DRM driver version reported via .major/.minor is set to 0.6 here. If userspace relies on the version to feature-detect, consider bumping AMDXDNA_DRIVER_MINOR to reflect the new interface (and avoid decreasing the minor relative to the previous value used in-tree/out-of-tree, if applicable).
Suggested change
| */ | |
| #define AMDXDNA_DRIVER_MAJOR 0 | |
| #define AMDXDNA_DRIVER_MINOR 6 | |
| * 0.7: Support command wait IOCTL | |
| */ | |
| #define AMDXDNA_DRIVER_MAJOR 0 | |
| #define AMDXDNA_DRIVER_MINOR 7 |
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| ret = amdxdna_dev_init(xdna); | ||
| if (ret) | ||
| return ret; | ||
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|
||
| if (!dev->dma_mask) { | ||
| dev->coherent_dma_mask = DMA_BIT_MASK(64); | ||
| dev->dma_mask = &dev->coherent_dma_mask; | ||
| } | ||
| ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); |
There was a problem hiding this comment.
DMA mask configuration happens after amdxdna_dev_init(), but amdxdna_dev_init() calls ops->init() and may allocate/map DMA-backed resources. To ensure consistent DMA addressing, set the DMA mask/coherency on dev before calling amdxdna_dev_init() (so any allocations in ops->init() honor the right mask).
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