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RISC-V sh2add not disassembled #8290

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Description

@CouleeApps

Version and Platform (required):

  • Binary Ninja Version: 5.4.9853-dev
  • Edition: Ultimate
  • OS: macOS
  • OS Version: 26.4
  • CPU Architecture: M1

Bug Description:
The following byte sequence is not disassembled: 20a6c6b3 (LE), b3c6a620 (BE) whereas riscv64-elf-objdump can disassemble it.

Steps To Reproduce:

  1. Open this file: firmware.elf.zip as rv32gc
  2. Navigate to 0x280a
  3. Observe undefined
  4. Python: Architecture["rv32gc"].get_instruction_text(b"\xb3\xc6\xa6\x20", 0x280a)
  5. Observe empty result
  6. riscv64-elf-objdump -d ./firmware.elf | grep -C5 280a
  7. Observe objdump gets it: 280a: 20a6c6b3 sh2add a3,a3,a0

Expected Behavior:
I expected all instructions to be disassembled properly

Binary:
firmware.elf.zip

Additional Information:
Source available if necessary. Probably more instructions not handled? I haven't checked too far after main didn't work. Apparently there are some places even objdump doesn't get (0x2604)... Weird that my toolchain can't disassemble the binary it can compile.

Board is a CH572D

Activity

  1. added theissue type on Jul 7, 2026
  2. CouleeApps commented on Jul 7, 2026

    @CouleeApps
    MemberAuthor

    This was addressed in 5.4.10005-dev via #7859. Opening the binary using Open with Options and selecting the rv32gc_wch platform correctly disassembles every instruction:

    Image
  3. added this to the Krypton milestone on Jul 7, 2026
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Arch: RISC-VIssues with the RISC-V architecture plugin

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