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Update output_to_verilog to inline temporary wires, using GateGraph:#471

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fdxmw merged 7 commits into
UCSBarchlab:developmentfrom
fdxmw:verilog
Jul 25, 2025
Merged

Update output_to_verilog to inline temporary wires, using GateGraph:#471
fdxmw merged 7 commits into
UCSBarchlab:developmentfrom
fdxmw:verilog

Clean up `output_to_verilog`'s newline logic. This simplifies the cod…

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