Gap
The RTU task-ring / XFR2TR interface is absent. The current two-core simulator
cannot express the hardware restriction or ring semantics, and IDs 0x70..0x72
currently fall through as unknown XFR operations.
Requested scope
Model the first bounded ring slice from AM64x/AM243x TRM Table 6-112:
- device IDs
0x70, 0x71, and 0x72;
- RTU_PRU-only access is enforced (PRU/TX_PRU access fails loudly);
- a bounded producer/consumer ring with empty/full status and deterministic
core-visible transitions;
- two-core integration tests that prove delivery, ordering, empty/full, and
a rejected access from an unsupported core.
This is intentionally separate from generic scratchpad and broadside FIFO
models: its value is the core-placement restriction as well as the data path.
Gap
The RTU task-ring / XFR2TR interface is absent. The current two-core simulator
cannot express the hardware restriction or ring semantics, and IDs
0x70..0x72currently fall through as unknown XFR operations.
Requested scope
Model the first bounded ring slice from AM64x/AM243x TRM Table 6-112:
0x70,0x71, and0x72;core-visible transitions;
a rejected access from an unsupported core.
This is intentionally separate from generic scratchpad and broadside FIFO
models: its value is the core-placement restriction as well as the data path.