Repository navigation
Conversation
…iCache write_through on rocm/sgl-dev v0.5.22
yichiche
added
the
full-sweep-fail-fast
|
Thanks for the contribution!
中文感谢你的贡献！
|
![claude[bot]](https://avatars.githubusercontent.com/in/1236702?s=60&v=4){kind=small}
|
View unofficial run (performance): https://inferencex.semianalysis.com/inference?unofficialRun=39763900198 View unofficial run (accuracy): https://inferencex.semianalysis.com/evaluation?unofficialRun=39763900198 |
yichiche
changed the title
yichiche
added
full-sweep-fail-fast
be1c914 to
00a128a
Compare
|
/reuse-sweep-run 39763900198 |
There was a problem hiding this comment.
As a PR reviewer and CODEOWNER, I have reviewed this and have:
- Verified that as of the moment of typing this, this is the latest version of PR_REVIEW_CHECKLIST.md
- Verified that the general code quality meets the InferenceX standard and does not make the code quality any worse.
- Verified that this PR has passed PR validation. Please link to GitHub Action workflow that shows this. Link: https://inferencex.semianalysis.com/inference?unofficialRun=39763900198
- Verified that this PR passes evals. Please link to GitHub Action workflow that shows this. Link: https://inferencex.semianalysis.com/evaluation?unofficialRun=39763900198
- Verified that speculative decoding PRs uses chat templates to align the AL distribution to real world
- Verified that every draft model and draft head is served as it ships: the draft that ships with the served checkpoint, at its stored precision, through the pinned upstream image's default handling, with the shipped and effective draft precision recorded in the additional detail section. No submission-side quantization, dtype override, checkpoint substitution, or patch may lower draft precision below that default, regardless of eval results or AL. Explicitly verified that
SGLANG_NVFP4_CKPT_FP8_NEXTN_MOEis not enabled in the effective recipe, including inherited settings; enabling it is prohibited going forward, and historical runs do not grant an exception. See Draft-model precision for what counts as the default and the MLPerf comparison. - For agentic workloads: verified that speculative-decoding configs (EAGLE / MTP / draft models) run with simulated synthetic acceptance, with the acceptance-length value taken from the committed golden AL curve in infx/golden_al_distribution/ for that model, thinking mode, and draft length. A submission may choose any supported draft length, but it may not substitute a different acceptance target.
- Verified against the current MODELS.md that this PR does not submit a deprecated model, scenario, or model-scenario combination.
- Verified that the model architecture isn't changed with benchmark hacks like using --hf-overrides to skipping indexer for every x layers on models that don't natively support this. As a general rule, we won't accept optimizations that reduces the number of model architecture FLOPs. Anything that makes that same computation run faster is fair game; target/verifier FLOPs at lower precisions is fine, given that the config passes private evals, but this does not permit lowering draft-model or draft-head precision below what ships. As an general north star princple, we should only use optimizations which is used in production by customers that care about accuracy
- For affected Dynamo TRT-LLM benchmarks, verified that iteration/KV-cache metrics are collected and published under the pinned Dynamo implementation and effective engine settings. Resolve the installed Dynamo version separately from the container tag; use supported metrics controls without requiring KV events. Record the version and configuration evidence in the additional detail section. See verifier Check 17. N/A for unaffected serving paths or frameworks without these Dynamo settings.
- If an company claims that they support vLLM/SGLang as first class LLM inference engines on their hardware, I have verified that the respective vLLM submission made using upstream https://hub.docker.com/u/vllm docker repo, upstream SGLang https://hub.docker.com/u/lmsysorg docker repo. The only exceptions are for new hardware, such as MI455X UALoE72, Vera Rubin NVL72, Rubin NVL8, etc., and for new model architectures where there is an actual reason why vLLM/SGLang does not fundamentally support them yet as supported by vLLM/SGLang community maintainers
- If an company claims that they support vLLM/SGLang as first class upstream in-tree LLM inference engines on their hardware, I have have verified that the respective vLLM/SGLang submission has been made before additional frameworks (TRT-LLM, ATOM, etc.). The only exceptions are for new hardware, such as MI455X UALoE72, Vera Rubin NVL72, Rubin NVL8, etc., and for new model architectures where there is an actual reason why vLLM/SGLang does not fundamentally support them yet.
- Verified that every affected vLLM/SGLang production serving configuration in this PR, including Dynamo deployments, is documented in the official vLLM recipes and/or the SGLang cookbook, for both single-node and multi-node aggregated and disaggregated serving. The documentation covers production-useful flags, environment variables, and launch commands (including prefill, decode, and router/frontend commands for disaggregation); InferenceX-only benchmark/harness settings are excluded with reasoning in the additional detail section:
- I linked the corresponding upstream PR in the vLLM recipe repo or SGLang cookbook source repo and verified that it is MERGED before this InferenceX PR merges. An opened, draft, or closed-without-merge upstream PR does not satisfy this requirement. If the matching recipe was already published, I linked the published recipe/cookbook page in the additional detail section below.
- Verified that this PR does not patch the inference engine or serving stack — the pinned image must run as shipped. This covers .patch files / git apply / patch, inline patches embedded in benchmark scripts (e.g. a python3/sed heredoc that rewrites installed engine sources before serving), in-place edits of site-packages, monkey-patching, overwriting container files, and installing forked/rebuilt engine wheels on top of the pinned image. The only exception is a patch covered by a filled-out waiver at docs/waiver/
<PR_NUMBER>.md— named after the PR that introduces the patch and filed in that same PR, stating what is patched, why the unmodified upstream image cannot run this benchmark, the upstream PR/issue link, and the removal plan — which I have linked below in the additional detail section. - If this PR uses
append-only: true, verified that it only adds generated points or recipe variants inside a selected existing config/scenario and existing same-image visual curve: every previously generated point remains present with the same recipe, no prior point is removed or rerun, and every benchmark-affecting change in the complete diff can affect only the corresponding newly appended points (never an existing point), regardless of which file contains it. - If any of the above criteria cannot reasonably be satisfied, I have provided additional reasoning below.
- Reported measured throughput/E2EL Pareto counts and evidence per affected curve (≥5 points strongly recommended). Below 5 or unverifiable: tag a core maintainer for review; recorded admin bypass required before merge. N/A if no curves are affected. Details.
Additional detail section:
Cookbook:
- sgl-project/sglang#46017
- sgl-project/sglang#46032
- sgl-project/sglang#46757 (add agentic section)
InferenceX-only exclusions:
enable-metricsandenable-cache-report: observability. They exposesglang:metrics and the cache-hit report for the AIPerf harness. They do not change serving behavior.SGLANG_TIMEOUT_KEEP_ALIVE=1800: client-pool keep-alive. It only outlasts AIPerf's 300 s client connection pool.PYTHONNOUSERSITE=1: container hygiene. It keeps the image from importing user site-packages.
Draft precision:
- The MTP head embedded in the served Qwen/Qwen3.5-397B-A17B-FP8 checkpoint. There is no separate draft checkpoint and the recipe sets no speculative-draft-model-path.
- Stored precision: block-FP8. weight_scale_inv is present on the mtp.* expert weights; mtp.fc and the MTP gates are listed in modules_to_not_convert and stay at the checkpoint's unquantized dtype.
- Default handling in the pinned image: lmsysorg/sglang-rocm:v0.5.22-rocm720-mi35x-20261020 loads the head natively. The recipe applies no draft path, no quantization override and no dtype override, so nothing is re-quantized or up-converted at load. SGLANG_NVFP4_CKPT_FP8_NEXTN_MOE is not set in the recipe and does not appear in the run logs.
- Effective serving precision: as stored — block-FP8 for the MTP experts, checkpoint dtype for mtp.fc and the gates. The draft shares the target's FP8 KV cache (kv-cache-dtype: fp8_e4m3) and no separate draft KV dtype is set.
Signed: @1am9trash
✅✅✅ Verdict: PASS ✅✅✅Passed and not applicable checks✅ Check 0 (CODEOWNER): PASS — ✅ Check 1 (Sweep on in-PR commit): PASS — in-PR commit ✅ Check 2 (Evals): PASS — gsm8k TP4 c80 on ✅ Check 3 (Upstream recipe): PASS — the three linked cookbook PRs, sgl-project/sglang #46017, #46032 and #46757, are all MERGED. Cookbook §3.3.1 (MI355X FP8 MTP agentic) matches every serving setting: the v0.5.22-20261020 image, the TP4 command, AITER environment variables and flags, fp8_e4m3 KV, chunked-prefill/scheduler/tokenizer tuning, EAGLE 3/1/4, watchdog, the per-concurrency max-running/graph-batch/hicache-size table, and the ✅ Check 4 (Reuse command): PASS — ✅ Check 5 (Latest checklist): PASS — all 18 items of the current ✅ Check 6 (Upstream image / ordering): PASS — the ✅ Check 7 (Deprecated models): PASS — on 2026-10-28, ✅ Check 8 (No architecture hacks): PASS — the recipe has no ✅ Check 9 (Chat template): PASS — the recipe sets ✅ Check 10 (No engine patches): PASS — the reachable path has no patches, setup scripts, source edits or engine wheel installs; the mi355x single-node lane defines no setup script. ✅ Check 11 (Agentic golden AL): PASS — the c80 throughput job applied ➖ Check 12 (Append-only): N/A — no new changelog entry sets ✅ Check 13 (Draft precision): PASS — the draft is the MTP head embedded in ✅ Check 14 (Pareto coverage): PASS — curve qwen3.5 / agentic-coding / mi355x_sglang / fp8 / p90 E2EL from run 39763900198 attempt 2 ( ✅ Check 15 (PR description): PASS — every body claim was recomputed from artifacts and matches. c80 cache-hit split: device 44.9% / host 49.1% / overall 94.0%, against baseline 50.2% / 43.3% / 93.5%. Throughput and latency: 60,839 vs 59,233 tok/s/GPU, p90 E2EL 47.9 vs 50.9 s, mean TTFT 2.68 vs 3.12 s, p90 ITL 31.1 vs 34.1 ms. Baseline ➖ Check 16 (NVIDIA overview): N/A — only MI355X (non-NVIDIA) configurations are affected. ➖ Check 17 (Metrics publication): N/A — this is a direct SGLang config with no Dynamo TRT-LLM serving path. ✅ Check 18 (Recipe/image/sweep consistency): PASS — no generation errors at the pinned SHA. The master entry and recipe agree (TP4, ep1, 19 concurrency points). The new image resolves to digest Assessed commit: |
yichiche
changed the title
|
@1am9trash Corrected, re-requesting verification. You were right on both counts: 51% was the GPU-tier share on run 36743632401 and ~95% was the overall rate on the new run, so the old claim compared two different metrics. I recomputed both runs from their
So the hit rate is flat and the real effect is a tier shift toward host DRAM, worth +2.7% per-GPU throughput and lower tail latency. Changes made in 786c796 and in the PR body:
No recipe or config change in this push; only the changelog text. |
|
Thanks for update. The CI is pass now. |
Summary
qwen3.5-fp8-mi355x-sglang-agentic-mtptolmsysorg/sglang-rocm:v0.5.22-rocm720-mi35x-20261020. The other MI355X Qwen3.5 arms stay on their current tags.hicache-write-policy: write_through_selectivetowrite_through. At concurrency 80 the overall prefix cache hit rate is flat (93.5% to 94.0%); what moves is the tier split, and per-GPU throughput gains 2.7%.Details
Correction to an earlier revision of this description
An earlier version of this PR body and of the changelog entry claimed the concurrency 80 cache hit rate "moves from 51% to about 95%". That comparison was not like for like: 51% was the GPU-tier-only share on the old run, and ~95% was the overall rate on the new one. Both numbers are now restated on the same metric. The claim has been corrected here and in
inferencex-e2e/perf-changelog.yaml.What the measurements say
Two runs, both at TP4 HiCache concurrency 80:
lmsysorg/sglang-rocm:v0.5.20-rocm720-mi35x-20260929,write_through_selective,hicache-size: 400.lmsysorg/sglang-rocm:v0.5.22-rocm720-mi35x-20261020,write_through,hicache-size: 374.Hit rates are computed from the SGLang server metrics in each run's
server_metrics_export.json, assglang:cached_tokensbycache_sourceoversglang:prompt_tokens.So
write_throughdoes not raise the overall hit rate — that was already ~94% underwrite_through_selective. It shifts where the hits are served from: the host DRAM tier backs a larger share of prompt tokens, the GPU tier a smaller one, and the net effect is a 2.7% per-GPU throughput gain with lower tail latency and TTFT.Caveat on the comparison
This is not a single-variable A/B. Between the two runs the image, the write policy, and the host pool size (
hicache-size400 vs 374) all changed, because the baseline run predates the host-pool tiering already onmain. The throughput and latency deltas above should be read as the combined effect of the image bump and the policy change, not as the isolated effect ofwrite_through.Scope of the recipe change
The same
write_through_selectivesetting was on every HiCache override from concurrency 16 through 80; all of them move towrite_through. GPU-resident points at concurrency 1, 4, 8, 12, and 14 do not enable HiCache and are untouched. HiCache sizes, the GPU-resident band, and the other MI355X arms stay as they are.Image
Docker Hub lists
lmsysorg/sglang-rocm:v0.5.22-rocm720-mi35x-20261020(HTTP 200). The tag was pushed 2026-10-20T14:52:20Z. The amd64 digest issha256:3a75c91365cc4f4e1194bf5d64b92f2f1ef134d8b9045da165fba28a8dada464. The previous canary onlmsysorg/sglang-rocm:v0.5.22-rocm720-mi35x-20261021died in the launch script (run 39638215045).AI model disclosure
Grok 4.7 prepared the original recipe edit, changelog entry, and description. Claude Opus 5 recomputed the concurrency 80 metrics from the two runs' artifacts and rewrote the cache-hit claim in this description and in the changelog entry. No delegated agents.