4th year ECE student passionate about RTL design and SoC design. I like taking silicon from spec to simulation — writing clean, verifiable RTL and chasing down bugs in waveforms until they make sense. Currently deep in RISC-V based SoC integration and digital verification workflows.
Languages
EDA Tools
RTL Design Writing synthesizable, clean SystemVerilog/Verilog for digital modules — from datapath and control logic to full block-level architecture.
Verification Building testbenches and test-vector generation flows to validate RTL behavior against spec, using EDA Playground for simulation.
SoC & Digital Systems Interested in processor integration, on-chip bus protocols, and how individual RTL blocks come together into a working system-on-chip.
RTL Design Verification SoC Architecture SystemVerilog Digital Design
⚡ Always debugging something — either RTL or life.