Remove the e-graph search now that synthesis replaces it

AGENTS.md

@@ -19,7 +19,7 @@
 - Exact SAT-based local placer, survey, and construct/compact pipeline: `docs/exact_local_placer.md`
 - Full-adder tiles that chain into n-bit ripple-carry adders (`CarryTiling`): `docs/carry_tiles.md`
 - Critical paths in redstone ticks: static timing, delay bounds, and timing-first construction and compaction: `docs/timing_driven_placement.md`
-- Equivalent NOR netlists from an e-graph (egg) with exact SAT extraction: `docs/egraph_netlists.md`
+- Equivalent NOR netlists from an e-graph (egg) with exact SAT extraction, an experiment record (the code was removed for exact synthesis) that also explains why wide-NOR construction steps time out: `docs/egraph_netlists.md`
 - Exact synthesis of NOR netlists that windowed construction can build (`exact::synthesize`, `nor_synthesis.rsdsl`): `docs/nor_synthesis.md`
 - Solver modeling DSL (rsdsl v2, crate `crates/rsdsl`): design and parity measurements `docs/solver_dsl_design.md`; grammar and language spec `docs/solver_dsl_grammar.md`; the exact placer's model is `src/transform/place_and_route/local_placer/exact/exact_placer.rsdsl` (grounded by `exact/dsl.rs`)
 

Cargo.toml

@@ -35,7 +35,6 @@ tracing-subscriber = "0.3.17"
 flate2 = "1.0.26"
 serde = "1.0.183"
 zip = { version = "2.2", default-features = false, features = ["deflate"] }
-egg = "0.9"
 
 [target.'cfg(not(target_arch = "wasm32"))'.dependencies]
 mimalloc = "0.1.43"

docs/egraph_netlists.md

@@ -1,5 +1,16 @@
 # Equivalent NOR netlists from an e-graph (2026-10-05)
 
+> **Status (2026-10-10): the e-graph code is removed.** Exact synthesis
+> (`nor_synthesis.md`) took its place. Synthesis designs a netlist and its
+> construction order together, proves minimum torch counts, and gave the
+> improvements (the 2-bit adder about a fifth smaller, the 4:1 mux built for
+> the first time). The e-graph's netlists were mostly unbuildable. Its lasting
+> results are the diagnosis below ("Why the steps fail") and the
+> `or_cost` 1 netlist, which synthesis found again. The measurements here
+> were taken at commit `600ad6d`, which still has `exact/egraph.rs`,
+> `exact/egraph_extract.rsdsl`, and the harness's `CIRCUIT=egraph-full-adder`
+> mode. The 8-gate netlist survives as `WIDE_FULL_ADDER` in `exact/tests.rs`.
+
 The exact placer builds the NOR netlist it is given. Construction places one
 gate per step, and the signal vocabulary is the netlist's net functions and
 their complements. A hand-written netlist such as the full adder's `nor9`
@@ -366,31 +377,27 @@ For the full adder in a 2-wide box:
 
 ## Running
 
+At commit `600ad6d` (the code is gone since):
+
 ```sh
 cargo test --release --lib egraph_netlists_compute_the_full_adder
 cargo test --release --lib explore_egraph_netlists -- --ignored --nocapture
 CIRCUIT=egraph-full-adder CIRCUIT_COMPACT_SECONDS=600 \
   cargo test --release --lib diagnose_construct_circuit -- --ignored --nocapture
 ```
 
-`explore_egraph_netlists` takes these knobs:
+`explore_egraph_netlists` took these knobs:
 
 - saturation: `EGRAPH_ITERATIONS`, `EGRAPH_NODES`, `EGRAPH_SECONDS`;
 - the sweep: `EGRAPH_MAX_DEPTH`, `EGRAPH_OR_COSTS` (comma-separated),
   `EGRAPH_BINARY=1`;
 - `EGRAPH_EXTRACT_SECONDS`;
-- `EGRAPH_GREEDY=1` also prints greedy extractions.
-
-The circuit harness takes `EGRAPH_DEPTH`, `EGRAPH_OR_COST`,
-`EGRAPH_BINARY`, `EGRAPH_SPLIT`, `EGRAPH_CHAIN`, and
-`CIRCUIT_ORDER=min-live`, besides the box and step knobs
-(`CIRCUIT_HEIGHT`, `CIRCUIT_MAX_WINDOW`, `CIRCUIT_STEP_SECONDS`,
-`CIRCUIT_RESTART_SECONDS`). `CIRCUIT_NETLIST_ONLY=1` prints the netlist,
-its live nets and its continuing inputs, and stops. The harness also prints
-each construction step: the gate, the input cases it is on in, its
-continuing inputs, and the nets alive after it.
-
-To see why a step times out, set `EXACT_DIAGNOSE_UNKNOWN=1` (with
-`EXACT_DIAGNOSE_VARIANT_SECONDS`, default 20). To solve that step again
-for longer and write it as DIMACS, set
-`EXACT_DIAGNOSE_FAILED_STEP=<prefix>` (with `EXACT_DIAGNOSE_SECONDS`).
+- `EGRAPH_GREEDY=1` also printed greedy extractions.
+
+The circuit harness took `EGRAPH_DEPTH`, `EGRAPH_OR_COST`,
+`EGRAPH_BINARY`, `EGRAPH_SPLIT` and `EGRAPH_CHAIN`.
+
+Still available: any netlist runs through the harness as text
+(`CIRCUIT=netlist CIRCUIT_NETLIST=...`, `CIRCUIT_CHAIN=<n>` for the support
+block stages), with `CIRCUIT_ORDER=min-live`, the box and step knobs, the
+per-step printout and the step diagnostics (`nor_synthesis.md`, "Running").

docs/nor_synthesis.md

@@ -182,3 +182,20 @@ CIRCUIT=netlist CIRCUIT_ORDER=index CIRCUIT_NETLIST='g3=NOR(cin); ...' \
 
 `CIRCUIT_NETLIST` takes `NorNetlist::to_text`'s form. A name read before it
 is defined is an input, and a net nothing reads is an output.
+`CIRCUIT_CHAIN=<n>` builds NORs of more than `n` signals in stages on one
+support block (`NorNetlist::chain_wide_gates`); a synthesized netlist has its
+OR stages already. Targets are expressions over the inputs (`~ & ^ |`,
+tightest first; `synthesis::truth_table`).
+
+The harness knobs: `CIRCUIT_HEIGHT`, `CIRCUIT_MAX_WINDOW`,
+`CIRCUIT_STEP_SECONDS`, `CIRCUIT_RESTART_SECONDS`, `CIRCUIT_ORDER`
+(`index`, `min-live`, smallest cone first otherwise). `CIRCUIT_NETLIST_ONLY=1`
+prints the netlist, its live nets and continuing inputs per gate order, and
+each construction step (the gate, the input cases it is on in, its
+continuing inputs, the nets alive after it), then stops.
+
+To see why a step times out, set `EXACT_DIAGNOSE_UNKNOWN=1` (with
+`EXACT_DIAGNOSE_VARIANT_SECONDS`, default 20): the first timed-out step is
+solved again with one requirement dropped at a time. To solve that step
+again for longer and write it as DIMACS, set
+`EXACT_DIAGNOSE_FAILED_STEP=<prefix>` (with `EXACT_DIAGNOSE_SECONDS`).