Name		Name	Last commit message	Last commit date
.gitignore		.gitignore
Assembly2Binaries.py		Assembly2Binaries.py
Assembly2Binaries_v2.py		Assembly2Binaries_v2.py
LICENSE		LICENSE
README.md		README.md
assembly_instructions.txt		assembly_instructions.txt
riscv_binary.txt		riscv_binary.txt
riscv_binary_v2.txt		riscv_binary_v2.txt

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Instruction_Binaries_Generate

generate bit stream for given RISC RV32I instructions

converts
Instruction -> 32-bit Binary

Ex:
add x3 x1 x2 -> 00000000001000001000000110110011

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generate bit stream for given RISC RV32I instructions

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