Sync upstream MLX and preserve Swift low-bit kernel support - #16
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Co-authored-by: Cheng <git@zcbenz.com>
Co-authored-by: hezz <hezz@example.com> Co-authored-by: Cheng <git@zcbenz.com>
…#3791) Co-authored-by: Pierre Lamy <pierre427@users.noreply.github.com> Co-authored-by: Cheng <git@zcbenz.com>
Co-authored-by: Cheng <git@zcbenz.com>
Co-authored-by: Cheng <git@zcbenz.com>
Co-authored-by: Cheng <git@zcbenz.com>
Co-authored-by: Cheng <git@zcbenz.com>
Co-authored-by: Cheng <git@zcbenz.com>
Co-authored-by: Cheng <git@zcbenz.com>
Co-authored-by: Cheng <git@zcbenz.com>
…ml-explore#4442) Co-authored-by: Cheng <git@zcbenz.com>
Co-authored-by: Cheng <git@zcbenz.com>
…xplore#4461) Co-authored-by: Pierre Lamy <pierrelamy427@gmail.com>
Co-authored-by: Cheng <git@zcbenz.com>
…xplore#4453) Co-authored-by: Cheng <git@zcbenz.com>
Co-authored-by: Cheng <git@zcbenz.com>
…ltiple of 32 (ml-explore#3912) Co-authored-by: Rohan Gautam <rohan1gautam@gmail.com>
…4497) Signed-off-by: Ranran Haoran Zhang <ranranhaoranzhang@gmail.com>
Co-authored-by: Yanzhao Wang <19340816+wyanzhao@users.noreply.github.com> Co-authored-by: Cheng <git@zcbenz.com>
…lore#4443) Co-authored-by: Dave Hind <davehind42@gmail.com> Co-authored-by: Anastasiia Filippova <a_filippova@apple.com>
…l-explore#4522) Co-authored-by: Anastasiia Filippova <a_filippova@apple.com>
Co-authored-by: Anastasiia Filippova <a_filippova@apple.com>
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| ring_.all_reduce<2, T, ReduceOp>(in_ptr, out_ptr, size, 1, reduce_op); | ||
| return; | ||
| } | ||
| if (n_bytes <= 32768 || count < size_ * 2 * n_conns_) { |
|
|
||
| // Mirror the all_reduce heuristics: use a single wire for small messages and | ||
| // scale up to n_conns_ wires for large ones where bandwidth dominates. | ||
| if (total < size_ * 2 * n_conns_ || n_bytes <= 65536) { |
| wire_offset[lr] = lr * n_wires * size_per_wire + | ||
| static_cast<int64_t>(lw) * size_per_wire; | ||
| int64_t region_end = | ||
| std::min(chunk_size, (lr + 1) * n_wires * size_per_wire); |
| wire_offset[lr] = lr * n_wires * n_bytes_per_wire + | ||
| static_cast<int64_t>(lw) * n_bytes_per_wire; | ||
| int64_t region_end = | ||
| std::min(n_bytes, (lr + 1) * n_wires * n_bytes_per_wire); |
| for (int lr = 0; lr < MAX_DIR; lr++) { | ||
| wire_offset[lr] = lr * n_wires * size_per_wire + | ||
| static_cast<int64_t>(lw) * size_per_wire; | ||
| int64_t region_end = std::min(chunk, (lr + 1) * n_wires * size_per_wire); |
bri-prism
marked this pull request as ready for review
September 22, 2026 20:20
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|
@khosravipasha could you take a look at this sync when you get a chance? On the CodeQL notes: all five are in |
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Merge current upstream MLX into the Prism branch while preserving the low-bit paths needed by the Swift runtime. This restores bias-free affine dispatch, carries the 1-bit wide loads, and corrects symmetric Metal buffer indices for upstream's reserved argument slot.
The source integration also retains the Prism NAX architecture guard and low-bit correctness fixes. Swift's generated sources and submodule pin are updated in the dependent Swift integration PR.
Validation of core
4fc91df60da3c313fe39bcaf34483b18c875efcathrough a clean checkout of Swift PR #8: 22 selected Metal runtime tests and 5 loader tests passed, including real packed Qwen3.5 text/vision logit comparisons. CUDA and iOS hardware were not tested.