Feature/csr - #7

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PeterWang-dev wants to merge 18 commits into

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Commits on Mar 12, 2026

refactor(hw/riscv/Rvi): rename Rvi to Rv32i to match the spec
PeterWang-dev
committed
13fcdbd

Commits on Mar 13, 2026

Commits on Mar 14, 2026

feat(hw): implemented ecall, csrrw, csrrs, mret
PeterWang-dev
committed
8226281
chore(hw/execute/CsrHandler): correct Spinal HDL triggered bug description
PeterWang-dev
committed
cfb80eb
chore(hw/debug): rename int regs debug signal
PeterWang-dev
committed
f6cffa6
feat(hw): add debug signals for csr registers
PeterWang-dev
committed
f1f689a
fix(hw/riscv/Privileged): correct encoding of mret
PeterWang-dev
committed
5ab15e4
feat(sim/rust): add csr support for difftest
PeterWang-dev
committed
2659095
fix(hw/execute/CsrHandler): fix mret datapath and bypass mstatus logic
PeterWang-dev
committed
32d27ca

Commits on Mar 27, 2026

fix(hw/blackbox/MemDpi): align dpi memory to axi-like interface and make read invalid when write
PeterWang-dev
committed
6e80c4d

Commits on Mar 28, 2026

feat(sim/rust): enhance diff result and disable difftest temporarily
PeterWang-dev
committed
d29898e

Commits on Jun 4, 2026

Commits on Jul 12, 2026

fix(sim/rust/futurecore): correct difftest skip sync write logic
PeterWang-dev
committed
ba93a30