[dimerr]

The V831 image from openipc-allwinner printed nothing on a real camera (8 MiB SPI NOR, flashed at 0x0). This PR makes it boot and speeds up the SPI NOR.

Boot

The SPL hung in clock_init(), before the console. QEMU models neither the PLL output gates nor the real reset values, which is why the bench never showed it.

• clock_init_safe() for V831/V833 now follows boot0's sunxi_board_pll_init() in order: CPU dividers while still on OSC24M, PLL_PERI0 read-modify-written and with its output enable, bus factors before their source, PLL_CPUX with its output enable (bit 27).
• SPL stack moved to SRAM C (0x58000), where boot0 keeps its own. 0x118000 in SRAM A2 was copied from the H6.
• NOR images: the eGON image is 32 KiB long, as boot0's is (build.sh).

These went in together. PLL_CPUX bit 27 plus the stack move alone was still silent; the full set boots. The individual cause was not isolated further.

SPI NOR

The controller node had no spi-max-frequency, so spi-sunxi clamped every transfer to its 1 MHz default, whatever SF_DEFAULT_SPEED said. The firmware scan took over 30 s on an empty flash. It is now 12 MHz on the bus (CCR 0x100b -> 0x1000).

Tested

	V831	V833
Real hardware	SPL, DRAM 64 MiB detected, U-Boot, SF, env; scan much faster	not tested
qemu-bench, this branch	boots to the prompt, CCR = 0x1000	boots to the prompt, CCR = 0x1000

The image tested on hardware had temporary UART markers in the SPL, removed here; this exact build has run under QEMU only. A kernel has not been booted on real hardware yet. V3s and V851s build and reach the prompt under QEMU; their clock path is unchanged.

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PR Summary by Qodo

Boot V831/V833 on silicon and run SPI NOR at 12 MHz

🐞 Bug fix ✨ Enhancement 🕐 40+ Minutes

AI Description

• Reorder V831/V833 SPL clock initialization and move its stack to SRAM C to address silent boots.
• Produce 32 KiB NOR eGON images to match the boot0 image length tested on silicon.
• Raise SPI NOR transfers to 12 MHz to shorten firmware scans.

Diagram

graph TD
  NOR[("SPI NOR")] --> SPL["eGON SPL"] --> SRAM[("SRAM C")] --> INIT["Clock init"] --> CPU["CPU PLL"] --> PERI["PERI PLL"] --> BUS["Bus clocks"] --> UBOOT["U-Boot SPI"]
  UBOOT -->|"12 MHz reads"| NOR

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High-Level Assessment

The following are alternative approaches to this PR:

1. Parameterize the shared H6 clock path

• ➕ Could reduce duplicated initialization logic across SoCs.
• ➖ V831/V833 require a different operation order and preservation of PLL reset-state bits.
• ➖ Changes to the shared path would increase regression risk for other SoCs.

Recommendation: Keep the silicon-specific SPL clock path isolated as proposed; the required ordering makes a shared-path refactor riskier. Before treating the boot fix as fully verified, test the exact uninstrumented image on V831 hardware and test V833 hardware separately.

Files changed (6) +123 / -21

Bug fix (6) +123 / -21

sun8i-v831-openipc.dtsDeclare the SPI controller's 24 MHz limit +2/-0

Declare the SPI controller's 24 MHz limit

• Adds a controller-level spi-max-frequency so spi-sunxi no longer applies its 1 MHz default limit. The board's configured flash transfers can consequently run at 12 MHz.

arch/arm/dts/sun8i-v831-openipc.dts

clock_sun50i_h6.hRemove the V831 fixed PLL_PERI0 register value +0/-3

Remove the V831 fixed PLL_PERI0 register value

• Drops the V831 PLL6 default constant because the new initialization sequence modifies the register without overwriting reset-state bits.

arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h

clock_sun50i_h6.cInitialize V831/V833 clocks in boot0-compatible order +93/-14

Initialize V831/V833 clocks in boot0-compatible order

• Adds a V831/V833 SPL clock path that prepares CPU dividers, enables and locks the CPU and peripheral PLL outputs, and sets bus factors before switching sources. Preserves PLL_PERI0 register bits through read-modify-write operations while leaving the other SoCs' safe-clock path separate.

arch/arm/mach-sunxi/clock_sun50i_h6.c

build.shGenerate 32 KiB eGON images for V831/V833 NOR +16/-0

Generate 32 KiB eGON images for V831/V833 NOR

• Pads the raw SPL with 0xff and regenerates its eGON header for V831/V833 NOR builds, making the declared SPL image 32 KiB. MMC builds and other SoCs retain their existing image generation.

build.sh

v831_configPlace the V831 SPL stack in SRAM C and set NOR speed +6/-2

Place the V831 SPL stack in SRAM C and set NOR speed

• Moves the SPL stack from SRAM A2 to 0x58000 in SRAM C. Sets both default SPI flash and environment speeds to 12 MHz.

openipc/v831_config

v833_configPlace the V833 SPL stack in SRAM C and set NOR speed +6/-2

Place the V833 SPL stack in SRAM C and set NOR speed

• Applies the same SRAM C stack location and 12 MHz SPI flash and environment settings to V833.

openipc/v833_config

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Code Review by Qodo

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