docs(dn)-Ghala-Buarish-02/22/26 (#481)

Author: Ghqlq

src/design_notebooks/2026spring/gb2789.md

@@ -29,4 +29,9 @@ Ghala's Design Notebook: Processor Design VIP
 
 [ProcDesign Project repository](https://github.com/Ghqlq/ProcDesign) - New folder: lab-5
 
-**Discussion:** In lab 5 there isn't much to do so as an exercise for myself I created a simple working rtl design along with a C++ tb using Verilator.
+**Discussion:** In lab 5 there isn't much to do so as an exercise for myself I created a simple working rtl design along with a C++ tb using Verilator.
+
+## Week5: 02/16/26 - 02/22/26
+- Completed Onboarding labs.
+  
+**Discussion:**  Lab 7 discusses the subteams within the VIP. I am interested in the Core subteam, but open to help in other subteams in addition to the documentation. Our next step could be to test if the full system (Core, AMBA interconnect, and memory) can run together. In this process we would be able to identify problems we face and document the whole process.