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docs(dn): Simon Hu 2/22/2026 (#480)
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# Simon Hu - Design Notebook (Spring 2026)
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## Week 4
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### Comments:
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Understand the core of verification.
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One output is from the Verilator, and the other is from the testbench.
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### Work done:
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- revised the lab 3 and verified the testbench on exercise 2.
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- terminal respond:
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simonlinux@DESKTOP-8L3L3I6:/mnt/e/NYU/processerVIP/onboarding-lab-3/build$ ./exercise2
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Randomness seeded to: 2048508371
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===============================================================================
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All tests passed (404 assertions in 4 test cases)
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## Week 3
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### Comments:
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Since in Lab 3 repo lack of header file, I first installed the verilator. Expected install in linux environment.
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Recommend learning Verilator: https://verilator.org/guide/latest/
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### Work done:
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- revised the lab 2 and verified the testbench.
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- terminal respond:
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simonlinux@DESKTOP-8L3L3I6:/mnt/e/NYU/processerVIP/onboarding-lab-2/build$ ./dv/tests
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Randomness seeded to: 2918360953
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===============================================================================
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All tests passed (262654 assertions in 10 test cases)
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- onboarding lab 2 link: https://github.com/1fHu/onboarding-lab-2.git
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- finished onboarding lab 3
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### Core instructions:
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cd build
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cmake ..
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cmake --build .
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./dv/tests
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remember to add the testbench file to CMakeLists.txt
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e.g. add_executable(tests
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exercise1.cpp
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exercise2.cpp
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exercise3.cpp
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exercise4.cpp
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)
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## Week 2
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### Comments:
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Busy week with conference travel.

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