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Use captured module spans for source locations and the current function definition for generated types, arrays and wrapper calls. Add regressions using the assertion kernel from NVIDIA#1379 and a helper in another file. Co-authored-by: Melih Elibol <1884921+elibol@users.noreply.github.com> Signed-off-by: Arthur031221 <levi74108520963@gmail.com>
Signed-off-by: Melih Elibol <elibol@users.noreply.github.com>
DeviceBuffer::cast_elem, DeviceBuffer::cast_chunks, and Tensor::reinterpret reinterpreted device bytes as any element type of the right size and alignment, which let a u8 buffer become a DeviceBuffer<bool> or Tensor<bool> holding values other than 0 and 1 (NVIDIA#1506). The casts now require bytemuck::AnyBitPattern of their target, so bool is rejected at compile time, and bool implements DeviceCopy: a typed buffer holds valid values by construction, so bool buffers can be allocated, filled, launched, and read back like any other element type. cuda-core re-exports bytemuck, implements Pod for the DType newtypes, and enables half's bytemuck feature for f16 and bf16. The atomic wrappers in cuda-device are not Copy, so they cannot be AnyBitPattern. DeviceBuffer gains wrap_elem and peel_elem, bounded on bytemuck::TransparentWrapper, to view a scalar buffer as its atomic wrapper and back. cuda-device implements TransparentWrapper for its atomic types and Pod for its vector types, and the examples that cast into atomics use the new methods. Every example lock gains the bytemuck dependency of cuda-device. Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
…pression span Short-circuit boolean operations (`a && b`, `a || b`) generate deciding constants when the left-hand operand decides the outcome. Previously, `compile_bool_constant` created constants from synthesized `bool` type spans, resolving to fallback module-header locations. Pass the logical expression's span through `compile_bool_constant` and the shared constant builder (`compile_constant_from_exact_bounds`), ensuring the resulting constant operation receives the exact expression line while preserving inlined helper scopes and call chains. Add regression test in `debug_info.rs` verifying source line attribution and inline caller provenance for both direct and inlined expressions. Part of NVIDIA#1475. Signed-off-by: GiGiKoneti <gigikoneti@gmail.com>
Signed-off-by: Trent Nelson <trent@trent.me>
…nMode
`tileiras` accepts `--device-debug` only at optimization level 0, but
`CompileOptions` kept the level and the debug flag as independent fields.
Debug builds default to full debug, so adding only `.opt_level(3)` produced
`--opt-level 3 --device-debug`, which `tileiras` rejects at JIT time.
Replace `opt_level`, `device_debug`, and `lineinfo` with
`codegen: CodegenMode`, where `Debug` owns level 0 and
`Optimized { level, lineinfo }` covers the rest. Every value now maps to
flags `tileiras` accepts. `debug_info()` and `opt_level()` select a mode,
and the last call wins. The level-0 default rule in
`TileirasOptions::from_compile_options` is gone, and the frontend reads the
same mode to decide check hoisting.
Remove the `device_debug(bool)` and `lineinfo(bool)` setters, which
`debug_info()` covers. The cache key and entry header bytes are unchanged
for every mode; a test pins them against the previous encoding.
Signed-off-by: almightychang (Sam, Joochul Chang) <almightychang@icloud.com>
Nothing could switch an already-built application to a debug or sanitizer build without changing its code. Add three process-wide variables, read once per process: - CUTILE_JIT_DEBUG=none|line|full acts like `debug_info()` - CUTILE_JIT_OPT_LEVEL=0|1|2|3 acts like `opt_level()` - CUTILE_JIT_SANITIZE=memcheck|none acts like `sanitize_memcheck()` Each applies after the code's options, as if its setter were called last. `CompileOptions::with_jit_env_overrides()` applies them once before both compile stages, so the frontend's check placement and the `tileiras` flags always come from the same options. Invalid values, and full debug together with an explicit level, return a JIT error naming the variable. This continues NVlabs/cutile-rs#237, which applied the overrides only to the `tileiras` flags and left the frontend hoisting checks under `CUTILE_JIT_OPTIMIZATION=debug`. Signed-off-by: almightychang (Sam, Joochul Chang) <almightychang@icloud.com>
Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
…nd SIMT Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
…uncher Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
Retain the source-scope map when line tables are enabled so native debug metadata includes inline call chains without variable debug info. Signed-off-by: Trent Nelson <trent@trent.me>
Check the file, definition line, subprogram and caller chain of the generated constants in the assertion kernel and in a nested cross-file helper, in Line and Full, and that the same locations are present in the serialized bytecode. A user literal in the same kernel must keep its own line. An opt-in test checks the cubin line table with nvdisasm and DWARF. Signed-off-by: Arthur031221 <levi74108520963@gmail.com>
…cesses Every override case now runs in a child process that inherits no CUTILE_JIT_* setting and is selected by a dedicated marker variable. The cases cover explicit none, line with an opt level, full, an invalid value, the full/opt-level conflict, and the read-once rule. The cache-key check compares keys reported by independent processes, each under its own overrides, so a key that dropped the effective mode would let two distinct modes collide. A GPU test runs the normal launcher against one shared disk store and checks the kernel result, the check placement, and whether stage 2 came from tileiras or the store. Signed-off-by: almightychang (Sam, Joochul Chang) <almightychang@icloud.com>
…eBuffers Signed-off-by: nihalpasham <nihalp@nvidia.com>
…viceBox::from_raw_parts and update docs Signed-off-by: nihalpasham <nihalp@nvidia.com>
…NVIDIA#1602) Preserve source locations and inline caller chains for const-generic arrays, generated reduction bodies, and checks relocated to the host. Keep deduplicated check origins private to the compiler and render them through the existing diagnostic API. Part of NVIDIA#1475. The remaining frontend items and debugger/backend fixes remain tracked separately; this does not close the full source-location audit. Validated with the CPU/assembler suites, source-location regressions, live CUDA-GDB tests, GPU host-check enforcement, host/Tile semver checks, and all 25 active CI checks on 825de3e. Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
…NVIDIA#1602) Preserve source locations and inline caller chains for const-generic arrays, generated reduction bodies, and checks relocated to the host. Keep deduplicated check origins private to the compiler and render them through the existing diagnostic API. Part of NVIDIA#1475. The remaining frontend items and debugger/backend fixes remain tracked separately; this does not close the full source-location audit. Validated with the CPU/assembler suites, source-location regressions, live CUDA-GDB tests, GPU host-check enforcement, host/Tile semver checks, and all 25 active CI checks on 825de3e. Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com> (cherry picked from commit 9718b43) Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
elibol
requested review from
kkraus14,
nihalpasham and
rparolin
as code owners
October 22, 2026 22:49
…py (NVIDIA#1516) Closes NVIDIA#1506. First change under NVIDIA#1460; implements the `bool` decision recorded there and in NVIDIA#1461 and NVIDIA#1503. Safe element casts previously checked size and alignment but could turn a byte containing `2` into a Rust `bool`. This PR rejects those casts, supports initialized `bool` buffers, and closes the host-side initialization, atomic-reference, kernel-argument, and pinned-alignment holes found during review and follow-up auditing. ## Element validity `DeviceBuffer::cast_elem`, `cast_chunks`, `can_cast_chunks`, and `Tensor::reinterpret` require `bytemuck::AnyBitPattern` on the target. Casting into `bool` is therefore a compile error. The two safe buffer casts also require `T: bytemuck::NoUninit` on their source: padding or `MaybeUninit` bytes must not become initialized destination values. `can_cast_chunks` remains a layout query. These bounds do not restrict `DeviceCopy` itself, and bool-to-byte casts remain supported. `bool` implements `DeviceCopy`: valid values can be copied between host and device, and its all-zero representation is valid. `DeviceCopy` does not promise that every bit pattern is valid. It remains independent of `DType`. The numeric `DType` newtypes implement `Pod`, and `half` enables its bytemuck feature, preserving numeric reinterpretation targets. cuda-core re-exports `bytemuck` for downstream marker implementations. Vector types in cuda-device also implement `Pod`, preserving `cast_chunks` usage. ## Owned atomic-buffer conversions `wrap_elem` and `peel_elem` use the unsafe marker `DeviceRepr<Inner>`. Its contract requires identical layout, valid initialized representations in both directions, no element destruction, and no additional ownership obligations. It has no methods and grants no reference conversions. The integer and floating-point atomic macros implement `DeviceRepr`, not `TransparentWrapper`. Consequently, safe `DeviceAtomicU32::wrap_ref(&u32)` and the reverse `peel_ref` conversion are unavailable. Owned scalar buffers can still be wrapped for atomic kernel access and peeled for readback, retaining their allocation, context, and deallocation stream. Kernel accesses must obey the existing borrowing and synchronization contracts. The marker lives in the dependency-free, `no_std` cuda-repr crate and is re-exported by cuda-core and cuda-device. This lets both sides share one trait without making kernel-only crates depend on the host runtime. The dependent lockfiles add this local package without changing registry or git dependencies. CI path filters include the new crate. The atomic examples use `wrap_elem`/`peel_elem`. `KernelSliceArg` is not restricted to `DeviceCopy`, since atomic wrappers are legitimate kernel element types that cannot implement `Copy`. ## Completed zero-initialization `DeviceBuffer::zeroed` queues the zero-fill and synchronizes its stream before returning. A safe readback or launch on another stream can therefore rely on initialization having completed, including for `bool`. Empty allocations retain their fast path. This makes nonempty `zeroed` a blocking constructor. Asynchronous initialization with automatically retained completion dependencies belongs to the subsequent runtime work; callers are not asked to repair a safe API through manual synchronization. ## Host-side argument contracts and pinned alignment `KernelInputStored` and `KernelOutputStored` now require `unsafe impl`. Their contracts cover truthful dtype/layout/specialization metadata, argument ABI, addressable extent, and storage/access retention through completion and graph replay. Previously an entirely safe custom binding could present `Tensor<bool>` storage as `u8` output, so a normal byte kernel could write invalid bool values. The input counterpart could similarly mislabel arbitrary byte storage as booleans. The safe `KernelInput`/`KernelOutput` conversion traits remain available and must return stored bindings satisfying those contracts. Existing owned, borrowed, view, and mapped bindings retain their behavior. `PinnedHostBuffer` reserves alignment slack, exposes an aligned interior pointer, and retains the original CUDA pointer for deallocation. It also rejects allocation sizes that exceed Rust slice/pointer-arithmetic limits. Empty and zero-sized buffers keep their aligned dangling pointers and allocation-free behavior. ## Tensor alias accounting Tensor aliases and lazy copy operations share a separate ownership token. Completion leases retain the storage itself without contributing to that token. Uniqueness therefore stays correct while a lease is being registered or destroyed: a real alias cannot become a mutable partition, and retiring a lease cannot spuriously reject a unique tensor. Access exclusion and completion retention remain enforced. The acquisition and destruction regressions fail on the previous implementation and pass with this change. A separate test preserves ownership held by an unsubmitted copy operation. ## Compatibility and validation The new `AnyBitPattern` target and `NoUninit` source bounds are breaking changes for safe casts whose element types do not implement those traits. Numeric targets remain supported; atomics use the owned-buffer conversions. Tuple types remain usable as buffer elements but are not reinterpretation targets. Custom stored Tile argument implementations must now explicitly uphold the documented unsafe contract. Earlier validation of the underlying changes: - Full cuda-core and cuda-device tests, including GPU buffer tests, compile-fail tests for invalid bool casts and both atomic shared-reference conversions, and layout checks for all 21 scoped atomic types. - A gated-stream regression that fails without the initialization synchronization and passes with it. It inspects bytes, avoiding invalid Rust bool values in the failing case. - Owned wrapper roundtrip coverage for pointer identity, context, stream retention, and readback. - GPU runs of `legacy_atomic_rmw_cas`, `legacy_atomic_fadd`, and `hashmap` on an RTX 5090; all six Tile tensor reinterpretation tests. - Clippy for cuda-core/cuda-repr, cuda-device/cuda-host, and cutile; host and component formatting; cuda-core/cuda-repr rustdoc with warnings denied. - Device-only build, example lock consistency, dependency-license/SPDX/source-reference/test-matrix guards, and cargo-deny for the host, SIMT, backend, device-only, and Tile workspaces. The Tile UI snapshot now uses the normalized external-crate path. Both UI harness tests (all 12 compile-fail cases) pass, and the CPU CI script now runs them. The version-only update to the planned v0.5.0 API boundary has landed on main in NVIDIA#1614; host and Tile semver checks pass. SIMT workflow branch filters now include stacked PRs targeting `pull-request/<n>` prerequisite mirrors. Follow-up validation for the host-side argument and pinned-buffer fixes: - Both new compile-fail cases compiled before the fix and now fail specifically because `unsafe impl` is required; snapshots were reviewed and rerun without overwrite. - The pinned alignment regression failed before the fix, without constructing misaligned references. It now passes, alongside over-aligned copying, empty/ZST coverage, and allocation-size boundary tests. - Full cuda-core suite: 105 passed, 3 ignored. Selected Tile library/GPU/tensor/view suites: 168 passed, 2 ignored. Submission-lifetime suite: all 9 passed, including forgotten borrowed work and graph replay. - cuda-core and cutile Clippy with warnings denied, host/Tile formatting, and SPDX checks passed. cuda-core rustdoc with warnings denied passed. Tile documentation builds, but its stricter warnings-as-errors check reports 12 existing link warnings outside the added trait documentation. Earlier host-argument follow-up validation: the complete CPU runner passes (1,408 tests, 98 intentionally ignored), including the Tile UI suites. All 25 targeted GPU buffer and pinned-host-buffer tests pass, including the cross-stream initialization regression. The branch includes the NVIDIA#1602 debug-source fixes and the same version metadata as NVIDIA#1614. Current validation (2026-10-30): head `117205c1277a9e6d422df20499342690b412bc16` includes main through `76ac10216`. The new regression fixture compiled before the source-validity fix, then all five trybuild cases passed afterward without snapshot regeneration. The new-main `math_special` example lockfile includes the host dependencies at the versions used by other examples; the full example dependency-policy guard passes. Fresh CI is running. GitHub dismissed the previous approval after the source changes, and renewed review has been requested. The expanded atomics example from current main uses owned `wrap_elem`/`peel_elem` conversions, with explicit checked ownership transfer for its standard-library atomic case. Strict example Clippy passes, and all 24 runtime atomic cases pass on both this PR and the combined shared-host stack on RTX 5090 / CUDA 13.3. Merge-readiness refresh (2026-10-30): head `c5ea583c5b5f06b424a9ab0c48174c771e99ff52` includes main through the merged NVIDIA#1480 (`b025a8b31`). The only manual conflict resolution preserved both changelog entries; source and tests from NVIDIA#1480 merged unchanged. The combined release candidate has an identical source/test tree to previously validated `c6c5a860a` (only the changelog and merge ancestry changed). New-head CI is running. Merge NVIDIA#1516 into main first, then retarget NVIDIA#1603 to main and merge it, then retarget NVIDIA#1604 to main and merge it. Do not merge the children into the temporary `pull-request/*` bases. Issue/release inclusion tracking: NVIDIA#1606. --------- Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com> Co-authored-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
…tree Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
…nd SIMT (NVIDIA#1603) Tile and SIMT currently expose separate `cuda-core` contexts, streams, launch configurations, and allocation owners. A buffer moving between the models consequently needs raw-pointer adaptation, and the separate runtimes cannot coordinate lifetime or conflicting accesses. This removes `cuda_core::simt` and gives both models the same host handles and allocation owner. `Device` identifies a physical GPU; `Context` owns or borrows the actual CUDA context. Typed buffers, contiguous sliced views, foreign owners, and Tile tensors share allocation identity and access tracking. `Tensor::from_buffer`, `into_buffer`, and `as_buffer` transfer or borrow storage without copying device memory. Ownership transfer rejects live typed aliases, preserving the boolean representation guarantees in NVIDIA#1516. Safe submissions retain allocations and access leases until GPU completion, including after a borrowed launch future is dropped or forgotten. Shared references to device atomics are conservatively tracked as writable. Buffer and stream destructors retire work without waiting on the dropping thread; unknown completion retains resources instead of freeing active memory. The existing SIMT async launcher receives the small retention bridge needed to make this core migration safe before its separate consolidation. Allocation uniqueness counts user-visible byte views independently of completion leases. This removes the retirement window where a decremented lease count still had a live Arc and made a unique buffer appear aliased. The same separation at the Tensor layer comes from NVIDIA#1516; both checks remain required for zero-copy ownership transfer. Nihal's fixes preserve ordinary shared-read permissions on empty and peeled buffers and wait for retirement before checking reclaimed VRAM. Consumer code, generated launchers, examples, templates, documentation, tests, and CI paths use the shared API. Tile numeric storage wrappers also implement `DeviceCopy`; `DType` and `DeviceCopy` remain independent traits. Stack: NVIDIA#1516 merged into `main` as `dfea11698aa63b9a42d9f8181a711d27774d0722`. This PR now targets `main` and contains only the core migration. Merge this before the follow-up NVIDIA#1604, which removes `cuda_async::simt`. Validation: - Full `cuda-core` suite: 111 passed; full `cuda-async` suite: 151 passed. - Selected Tile library/GPU/interop/submission-lifetime suites: 156 passed, including graph replay, offset preservation, alias rejection, and forgotten futures. - SIMT host/macro suites: 261 passed; cargo-oxide: 268 passed. Three additional GPU launch-lifetime regressions pass explicitly with `--ignored`. - Clippy with warnings denied for host workspace, Tile, and affected SIMT packages; strict cuda-core rustdoc; formatting, host-path and SPDX guards. The Tile workspace is also checked with every example feature enabled, including Candle CPU references. - Dependency checks pass for the host, SIMT, backend, device-only fixture, and Tile workspaces. GPU validation used a single RTX 5090. Multi-GPU/NVLink cases self-skip on this machine; this does not claim multi-GPU coverage. Existing deliberately ignored tests remain ignored. Closes NVIDIA#1460. Closes NVIDIA#1504. The global-context re-entry/state-machine follow-up remains tracked separately in NVIDIA#1403. Earlier follow-up validation: all 50 cuda-core unit tests and all nine targeted shared-allocation/retirement GPU tests pass, as does cuda-core Clippy with warnings denied. The new concurrency regression failed 3,308 uniqueness checks on the previous implementation and passes with the fix. Earlier main integration: Merged the updated NVIDIA#1516 prerequisite and migrated the new CuTe host consumers to shared LaunchConfig and the explicit event-flags API. Affected-package Clippy and all 16 CuTe example/model workspace Clippy checks pass. CI passed before this refresh; current-head CI is tracked below. Current update (2026-10-30), head `98d0820debc6f3994cb45c041ac182e174bff364`: Plain completion leases now retain allocation access independently of user-view tokens, so tensor-to-buffer conversion preserves unique ownership without weakening cross-stream exclusion or recorded graph ownership. The combined stack passes 1,427 CPU/assembler tests, 750 GPU tests, 27 supported examples and eight benchmark smoke tests. Initial disk exhaustion was resolved and the affected suites rerun successfully. The expanded atomic example is migrated to owned conversions; all 24 atomic GPU cases also pass on the final shared-runtime head. Fresh CI is running; NVIDIA#1516 still needs renewed approval before this stack can merge into main. Merge status (2026-10-30): current head `ba76442278ad1d6c67070ef5fde3dd63efcddb85` records the accepted NVIDIA#1516 squash merge. The squash-merge tree exactly matches the accepted NVIDIA#1516 head; the ancestry-only refresh leaves this PR's entire file tree unchanged from its reviewed predecessor. After copy-pr-bot deleted the old temporary bases and automatically closed the stacked PRs, they were reopened against `main`; temporary restoration refs were removed. Merge order is NVIDIA#1603 then NVIDIA#1604. Fresh CI is running, and retargeting caused GitHub to require review again. Issue/release tracking: NVIDIA#1606. --------- Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com> Signed-off-by: nihalpasham <nihalp@nvidia.com> Co-authored-by: Melih Elibol <1884921+elibol@users.noreply.github.com> Co-authored-by: nihalpasham <nihalp@nvidia.com>
…d async tree Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
Tile operations and SIMT launches currently use separate async runtimes and cannot compose through the same operation types. This change removes `cuda_async::simt` and routes both programming models through the shared `DeviceOp`, `DeviceFuture`, execution context, scheduler, errors and launch API. Closes NVIDIA#1461. Prerequisite NVIDIA#1603 is merged into `main` as `6a6372e4cc2e0f142471cf18f13b9072abe87757`. This PR targets `main` and its diff now contains only the async migration. The development branch remains on the contributor's fork. - One `KernelArgument` blanket implementation uses `DeviceCopy`. Generic Tile scalars require `DType + DeviceCopy`; tensor-only type parameters retain their independent `DType` contract. The shared argument arena preserves inline storage, padded values, over-alignment and typed destruction for the explicit unsafe boxed-argument escape hatch. - An inert `AsyncKernelLaunchBuilder` requires unsafe finalization before becoming a schedulable, immutable launch. Generated typed launchers retain their checked boundaries. Tile PDL and SIMT cluster/cooperative launch paths are preserved. Raw async macros marshal slice pointers and lengths as direct scalar values; optional CPU-reference examples use the corresponding scalar bounds. - Launches retain their function/module, allocation owners and access leases before enqueueing work. Early future drop retires owners on completion without waiting on the GPU. Partial errors and panics retain submitted resources; unknown completion deliberately leaks owners and exclusion. Forgotten futures also retain their submissions indefinitely. Outputs can contain ordinary Rust borrows and must be valid to drop during submission, as required by host combinators. - Graphs retain captured resources and reacquire allocation access on every replay. `DeviceBox` transfers to/from shared typed buffers without copying and preserves ordinary read permissions. Existing `DeviceOperation`, `and_then`, `apply` and `arc` spellings delegate to the shared implementations. - `cutile_inter_kernel` now uses the normal shared launch API to update the Tile-produced allocation in place, checks its pointer and allocation identity, and verifies results. Consumers, generated-project templates, documentation, UI fixtures and GPU test entry points are migrated. `AGENTS.md` records that future branches must originate from the user's fork. Validation: shared async tests and doctests; Tile unit, aggregate GPU, submission-lifetime, interop and UI tests; cuda-host/cuda-macros suites; 268 cargo-oxide tests; four explicit SIMT lifetime/concurrency GPU tests. Both `cargo oxide run cutile_inter_kernel` and `cargo oxide run async_mlp` pass. Miri passes all seven argument-storage tests, and Loom passes the completion-handoff model. Host/Tile/affected SIMT clippy checks, formatting, strict async rustdoc, SPDX/API-path guards and Tile dependency checks pass. GPU execution was validated on one RTX 5090. This does not add multi-GPU/NVLink hardware coverage. API migration and custom-operation retention obligations are documented in `cuda-async/README.md`. Additional validation: the full CPU runner passes (1,381 tests; 94 intentionally ignored), all top-level SIMT example workspaces pass Clippy with warnings denied, and all 144 macro unit tests pass. The `host_closure` GPU example also passes all 13 scenarios, covering the corrected async slice argument marshalling. Earlier follow-up validation after incorporating the updated NVIDIA#1516/NVIDIA#1603 stack: all 1,394 CPU tests pass (95 intentionally ignored), as do 138 selected Tile GPU/interop/graph/view/lifetime tests and all four explicit SIMT lifetime/concurrency tests. The original stress reproducer reports no false negatives in 1,000,000 raw-buffer uniqueness checks and no false positives in 100,000 aliased-tensor partition attempts. Nihal's `DeviceBox::from_raw_parts` shared-read fix remains included. Restored the original cutile-rs `unsafe async_on()` contract: the caller independently keeps all submitted resources alive and orders their accesses. On return, including an error, `async_on()` releases runtime owners and access leases without synchronization or background retention. Safe futures retain their nonblocking completion-based cleanup. The existing four-tensor launch benchmark now measures 1.88 µs/launch, down from 4.95 µs before this fix (earlier main baseline: 1.68 µs). No batching or new launch API is needed for this fix. Earlier main integration: Merged the updated NVIDIA#1603 prerequisite, including the CuTe host-consumer migration. The cuda-host, cuda-macros, ctm-rs and cute-rs suites pass (497 tests, 43 intentionally ignored), together with affected-package Clippy and all 16 CuTe example/model workspace Clippy checks. CI passed before this refresh; current-head CI is tracked below. Validation for `b811b7067`: all 133 cuda-async tests pass (14 intentionally ignored), all 11 Tile submission-lifetime tests and all four SIMT lifetime/concurrency GPU tests pass, and Clippy/formatting/rustdoc checks pass. Both new gated-stream regressions fail on the preceding code and pass here. That revision was validated before the current refresh. Current update (2026-10-30), head `95a51d708cc1dd203a922a28624aa087cb7a2176`: Carries the NVIDIA#1516 source-validity and NVIDIA#1603 completion-retention fixes while preserving the reviewed async launch lifetime/access contracts. The combined stack passes 1,427 CPU/assembler tests, 750 GPU tests, 27 supported examples and eight benchmark smoke tests. Initial disk exhaustion was resolved and the affected suites rerun successfully. The expanded atomic example is migrated to owned conversions; all 24 atomic GPU cases also pass on the final shared-runtime head. Fresh CI is running; NVIDIA#1516 still needs renewed approval before this stack can merge into main. Merge status (2026-10-30): current head `21bc9bb783429ef39da7ee9ac63bbd686a3a5895` records accepted NVIDIA#1603 squash ancestry. The squash commit's entire tree exactly matches the prerequisite head already included here (`ba7644227`). The apparent conflicts were duplicate history; this merge changes zero files relative to previously green `ede42672a`. GitHub reports the PR mergeable. Current-head CI has restarted; the previous identical tree passed all 70 applicable checks, including GPU tests (one expected skip). No test assertions were relaxed. The earlier intermittent drop-timing failure remains tracked as test-hardening follow-up NVIDIA#1680. Issue/release tracking: NVIDIA#1606. --------- Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com> Signed-off-by: nihalpasham <nihalp@nvidia.com> Co-authored-by: Melih Elibol <1884921+elibol@users.noreply.github.com> Co-authored-by: nihalpasham <nihalp@nvidia.com>
Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
## Summary Fixes NVIDIA#1518. Move the GitHub-hosted `ubuntu-latest` jobs onto `linux-amd64-cpu4` (`m7i.xlarge`, 4 vCPU / 16 GiB), the same size as `ubuntu-latest`. Tile test jobs in `cutile-rs.yml` already run on `linux-amd64-cpu16` and stay there. `book.yml`'s `deploy` job stays on `ubuntu-latest`, because `actions/deploy-pages` publishes GitHub Pages from a GitHub-hosted runner. --- > Questions about the review? Ping us in [#contributors on Discord](https://discord.gg/ZUEr4AhH5C). --------- Signed-off-by: Roman Ivanov <rivanov@nvidia.com>
…NVIDIA#1541) ## Summary Fixes NVIDIA#1540. `TensorView::view` computed its specialization from the allocation base and dropped `offset_bytes`, so a view over a slice that starts off a 16-byte boundary claimed 16-byte alignment. The JIT then emitted vectorized loads and the launch failed with CUDA error 716. The view now passes `base + offset_bytes`, as both `slice` methods already do, so such views report their real alignment and get their own kernel cache entry. ## Changes - `cutile/src/tensor.rs`: add `self.offset_bytes` to the pointer passed to `compute_spec` in `TensorView::view`. The other `compute_spec` callers build specs for `Tensor`, which has no offset, or already add it. - `cutile/tests/tensor_views.rs`: a host-only test asserting `base_ptr_div` on a view of an offset slice, and a GPU test that copies that view with 32x32 tiles, the shape that triggers vectorized loads. - `CHANGELOG.md`: a `### Fixed` entry under `[Unreleased]`. The first commit adds the tests; the second is the fix. ## Testing Run on an RTX 4070 Ti SUPER (sm_89), driver 615.78.08, tileiras 13.4. - Without the fix, the GPU test fails with `DriverError(716, "misaligned address")` and the spec test sees divisor 16. - With the fix: - `cargo test -p cutile --test tensor_views`: 17 passed. - `cutile-rs/scripts/run_cpu_tests.sh`: all CPU tests passed (65 test binaries, 0 failures). - `cargo fmt -- --check`: clean. - `cargo clippy --workspace --exclude cuda-tile-rs --all-targets`: exit 0. The one warning is in `cutile-benchmarks` (rmsnorm), which this PR does not touch. - [ ] `just -f cuda-oxide/Justfile check` passes. N/A, no SIMT changes. - [ ] `cargo oxide run <example>` passes. N/A, no SIMT changes. - [ ] New example added (if applicable). N/A. ## Checklist - [x] All commits signed off (`git commit -s`) - [x] SPDX headers on new source files (no new files) --------- Signed-off-by: Younes <git@younes.io>
The two FP8 execution tests in `dtype_float_ops` currently attempt to compile FP8 kernels on targets below sm_90, where the compiler correctly rejects them. Check the existing `Feature::Fp8` capability before allocating either tensor, so unsupported targets print the standard skip diagnostic while supported targets still run creation, conversion, and numerical checks. Toolkit discovery failures and JIT/execution failures remain test failures. The four other float tests are unchanged. Validation: - `cargo test -p cutile --features experimental-tune --test dtype_float_ops -- --nocapture`: all six tests pass on RTX 5090 / CUDA 13.3, including both FP8 execution paths. - `cargo fmt --all -- --check` and `git diff --check`: pass. - `scripts/run_all.sh`: CPU/assembler and GPU suites pass; 27 examples pass with one expected toolkit-dependent skip; all eight benchmarks pass. - The existing IR requirements suite passes, including feature checks across sm_80 and supported FP8 targets. An sm_80 hardware rerun is still needed to confirm the skip in the full GPU suite. Target release: cuTile Rust v0.5.0. Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com> Co-authored-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
…VIDIA#1634) ## Summary `scripts/test_benchmarks.sh` calls ```bash run_benches "$REPO_ROOT/cutile-benchmarks/benches" "smoke-test" ``` Since `run_benches` was changed to parse cargo flags, it takes `--features X` and drops every bare word. So `smoke-test` never reaches Cargo. `run_all.sh` and the README's "fast, discards results" smoke test then run every benchmark with full criterion settings. They also save `base` baselines, which the smoke mode is meant to leave alone. The script's output is discarded, so nothing shows this. ## Changes - `test_benchmarks.sh`: pass `--features smoke-test`. ## Testing B300, softmax bench, run the way `run_benches` runs it: ```text before (argument dropped): exit=0 19 s "Warming up for 500.00 ms" x6 after (--features smoke-test): exit=0 9 s "Warming up for 1.0000 ms" x6 ``` With the fix, `test_benchmarks.sh` reports 4 passed / 4 failed on B300. The four failures (`fmha`, `fmha_causal`, `gemm`, `launch_overhead`) are unrelated to this change: on my host they come from a tileiras/toolkit version mismatch, which I am checking separately. - [x] bash syntax check - [ ] `just check` -- not run; script-only change ## Checklist - [x] All commits signed off (`git commit -s`) Signed-off-by: 0z5a <dezhen.lu@student.uni-tuebingen.de>
Merge main through NVIDIA#1541, NVIDIA#1683 and NVIDIA#1634. Resolve workflow conflicts using the accepted NVIDIA#1580 copy-pr-bot triggers. Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
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/ok to test dfd6867 |
Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
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/ok to test 54be19d |
Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
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/ok to test 2c01bfb |
Closes NVIDIA#1451 `api::full` currently uses unchecked multiplication to calculate its flattened element count. Invalid shapes can panic during construction or wrap before allocation and initialization, with shape validation occurring later during `reshape`. Validate the element count with checked multiplication and reject zero dimensions and flattened lengths above `i32::MAX`. Invalid inputs return `DeviceError::Internal` when the operation executes, before GPU allocation or kernel execution. `zeros` and `ones` inherit the validation through `full`. Add five host tests and three GPU tests covering overflow, zero dimensions, the `i32` boundary, construction without panics, and valid tensor shapes and values. Preserve scalar shape `[]`. ### Validation Run from `cutile-rs`: ```bash cargo fmt --all -- --check git diff --check cargo test -p cutile --lib api::full_shape_tests cargo test -p cutile --release --lib api::full_shape_tests cargo test -p cutile --test gpu tensor_guards::full_ cargo test -p cutile --release --test gpu tensor_guards::full_ cargo clippy -p cutile --lib --test gpu -- -D warnings RUST_TEST_THREADS=1 bash scripts/run_all.sh ``` All commands passed. The serial full run passed CPU and GPU tests, 24 examples, and all eight benchmark smoke tests. Three examples were skipped because they require newer Tile IR versions. The default parallel run failed in `warmup_composed::composed_builder_compile_terminal_warms_the_dispatched_specialization`, with a JIT compile count of 17 instead of 18. That test passed in isolation, and all 16 `warmup_suite` tests passed serially. These results suggest a cache state or test ordering dependency; no warmup code is changed in this PR. Signed-off-by: Raul Estrada <raulestradaa@gmail.com> Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com> Co-authored-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
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/ok to test e16b73a |
…NVIDIA#1684) Older bindgen can emit a one-byte placeholder instead of the fields of a forward-declared C struct when using libclang 22. This produces incorrect CUDA bindings and failing layout checks. Upgrade `cuda-bindings` to bindgen 0.72.1, which includes the upstream type-completeness fix in [rust-lang/rust-bindgen#3278](rust-lang/rust-bindgen#3278). The regression test uses a self-contained C typedef chain and verifies that both fields of the completed struct survive binding generation. With bindgen 0.69.5 and libclang 22 it fails because only `_address` is emitted; with 0.72.1 it passes. It runs as part of the existing `cuda-bindings` test suite. Use libclang 22 to exercise the original failure. The large diff is generated lockfile maintenance: 263 affected workspace/example lockfiles now resolve the updated shared bindings dependency. Package additions are limited to the new bindgen and its required rustc-hash version; obsolete transitive dependencies disappear. Archived benchmarks that use separately published crates are unchanged. Validation: - The regression fails with bindgen 0.69.5/libclang 22 and passes with 0.72.1/libclang 22. - Full `cuda-bindings` tests pass, including a CUDA 13.3/libclang 21 compatibility run. Bindgen now emits compile-time layout assertions, so validation includes compiling the generated bindings rather than filtering for old runtime layout-test names. - Shared-host workspace all-target checks, Tile all-target checks, 108 SIMT host tests, and SIMT codegen/Cargo frontend checks pass. - All 263 updated lockfiles resolve with `--offline --locked`; the example lockfile consistency gate also passes after aligning six existing rustc-hash pins with the other examples; dependency policy checks pass for the host, Tile, SIMT, backend, and device-only workspaces. - Formatting, strict bindings Clippy, license inventory, shared-crate pin, and SPDX checks pass. - The new binding-generation regression remains required in the CPU/build suite, which passes with libclang 22 (15 tests; two live-driver cases filtered). The archive-only GPU runner excludes that one compiler-dependent test because its image has no libclang. Reproduced the unfiltered failure in the CI CUDA 13.3.0 image, then verified all 16 runtime tests pass with the corrected filter, including live CUDA/cuRAND. - The head includes merged NVIDIA#1452; its five shape unit tests and three GPU regressions pass on the combined branch. Target: cuTile Rust v0.5.0. --------- Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com> Co-authored-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
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/ok to test d2c8120 |
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Integrate all accepted cuTile Rust v0.5.0 source fixes into
release/v0.5.xfor SWQA retesting.Current candidate:
d2c8120bf35ebb1fa1e6b9bb0b240f425a6fa91b. CI is green: 76 checks passed, one expected skip (deploy). The complete file tree matches accepted main at2d47e43e7437ca03cf84a469a9f54bfdcfb02c95exactly. This refresh records accepted main ancestry and removes a duplicate changelog entry; it changes no code, tests, dependency resolutions, or workflows relative to the preceding candidate.All source PRs are merged into main:
cuda_core::simt.cuda_async::simt.Validation and CI:
54be19d98; the binding implementation remains unchanged.e16b73a9chad one GPU CI failure:dropping_in_flight_future_returns_promptly_and_retires_ownerstook 200.853427 ms against its 100 ms assertion. This is the existing timing-based test tracked in tests: replace wall-clock correctness assertions and sleep-based race coordination #1680; its cause remains unresolved. The assertion has not been relaxed or skipped. The exact test passed 30/30 isolated local runs, and the full GPU CI suite now passes on the final candidate. No test or runtime changes were needed. The underlying timing-test follow-up remains open under tests: replace wall-clock correctness assertions and sleep-based race coordination #1680.SWQA handoff:
elibol/cuda-rust.release/v0.5.0-host-debug-integration.a8d91829faa6a64e10bf27cf817c7e9f7608fba7; updating this branch does not silently change SWQA's selected revision.bindgen_test_layout_*names is not validation.cuda_tile_assert!trap, cuda-gdb reports the module's first line and drops the inlined helper frames #1379 and uncovered portions of cuTile: audit generated source locations (optional follow-ups to #1379) #1475 remain open.Final CI is complete. Keep this PR draft until SWQA retest/sign-off is complete. The actual
release/v0.5.xbranch remains unchanged until this PR is merged. After accepted fixes reach that branch, #1606 tracks the reminder to request the internal CTK 13.5 profiling/debugging tests.