[TRTLLM-13767][feat] integrate FP4 Conv3d into parallel Wan VAE

[taianz-nv]

Summary

Integrate the Blackwell NVFP4 Conv3d kernel into the native Wan VAE and make the FP4 path compose with the existing parallel VAE wrapper.

This change:

• vendors the block-scaled CuTeDSL implicit-GEMM Conv3d kernel and its dynamic preferred-cluster scheduler;
• detects ModelOpt NVFP4 VAE checkpoints and converts eligible native Wan Conv3d modules automatically;
• prequantizes weights once and supports calibrated static or dynamic activation quantization;
• automatically fuses RMSNorm + SiLU + FP4 quantization when the calibrated static path and module structure permit it;
• always folds Conv3d bias into the kernel and uses the residual epilogue when the caller provides a shape-compatible residual;
• uses the 256x256, 2CTA, 2x1-cluster tactic selected for the parallel Wan shapes; and
• adds structural, composition, quantization-parity, and real B200 kernel tests.

There are no per-fusion environment variables or new public VisualGen API. Fusion selection is an internal implementation decision derived from the checkpoint, module structure, and parallel output contract. The BF16 path does not import or initialize the FP4 kernel.

Dependency

This PR requires the CUTLASS DSL 4.6.1 upgrade in #17274. The dependency and its optional-attention compatibility changes are intentionally absent from this diff.

Parallel-VAE scope

This PR is intentionally independent of the other parallel-VAE optimizations:

• It does not contain the halo communication/layout implementation from [TRTLLM-14555][perf] Optimize parallel VAE halo exchange path #17001.
• It does not contain the DupUp3D fusion from [TRTLLM-14798][perf] Fuse Wan DupUp3D output mapping #17003.
• Temporal batching is already present in main and is not part of this diff.

The current mainline halo wrapper delegates the pointwise RMSNorm/SiLU fusion capabilities, so FP4 Conv3d works in the parallel VAE. The rank-local residual remains unfused in the parallel path because mainline halo computes an expanded output and strips it after the convolution. Once #17001 lands, its local-width output contract can enable the residual epilogue without bringing the halo implementation into this PR. Bias fusion and the single-GPU residual epilogue are active here.

Validation

• Full changed-file pre-commit suite: passed.
• NSC B200 job 1619867:
  • 21 FP4 structural/composition tests passed.
  • 6 real GPU kernel tests passed, including automatic bias + residual fusion and asymmetric spatial padding through the product wrapper.
• The kernel reference checks cover output parity and a nonzero-convolution quality threshold.

Draft follow-ups

• Add the consolidated VAE-only/E2E performance and LPIPS table from the project report.
• Rebase after [TRTLLM-14555][perf] Optimize parallel VAE halo exchange path #17001 and enable the parallel residual epilogue when its local-width output contract is available.
• Run the target VisualGen CI stages before marking ready.