docs: fold the ROCm/gfx1151 GGUF arms in, rebased onto the consolidated tree - #331
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…ed tree Ports #326's content onto main after #327 merged. #326 was stacked on the closed #323 branch and would have re-added ocrbench_table.py, the renderer #327 deleted; its doc material is the part that was genuinely new, and it is here with the two names corrected — summarize_extbench.py is the surviving renderer, and manifest-digest identity is ADR 0038 after the renumber. The ROCm rows land as a third engine section: q4_K_M 171/200, q8_0 and bf16 169/200 each, with q8_0 and bf16 agreeing on every one of the 200 items. Flat ladder, different silicon, same conclusion as CUDA. It also corrects a claim this document made. ADR 0036's batch floor is a per-host fact, not a property of the build: the same commit asks for 2048 on both hosts, gets it on CUDA and is refused it on gfx1151, so a reader must check the logged num_batch rather than assume the floor applied. The shared index says so too, next to the seconds-per-item column that is likewise not comparable across hosts. The learnings entry keeps the AMD session's finding about the 9px tier — bf16 scores 4, nvfp4 on the fixed kernel scores 3, nvfp4 on the broken kernel scored 4, so ollama#3912 did not cost a tier, it stopped hiding one — and its independent discovery that gemma4:31b-mxfp8 carries a bf16 vision tower. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
#330 landed the same correction with the root cause named — availableMemoryForLoad takes its integrated-GPU branch on gfx1151 and sizes the batch against 31 GiB of system RAM while the scheduler logs 95.4 GiB of GPU. That is the better text. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
…py of the tables Main already carries the AMD host's own ladder doc, so folding its tables into the CUDA one would rebuild the duplication #327 removed. What was genuinely unique in #326 is the cross-host comparison, and that belongs where both hosts meet: ocrbench.md now states what differed between the two runs — context rung, repeats, one-batch against split decode, seconds per item — and what the pair supports that neither supports alone: the two hosts decoded the image differently and landed within two items of each other at every rung. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
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Rebase of #326 onto main after #327 and #330 landed, reduced to what is actually still missing.
Main already has the AMD host's own ladder document and, from #330, the gfx1151 batch-floor correction with its root cause. Copying #326's tables into the CUDA document would rebuild the duplication #327 removed, so they are not copied.
What this adds instead:
resolved: norather than an ordering when a pair does not clear the test, and the note that three sessions wrote a renderer for this within a day and two were dropped, which is SPEC H1 applied to summarizers.The 9px tier finding and the mxfp8 bf16-tower trap from #326 are already in main via #330.
Supersedes #326.
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