A 112 × 158 mm 8051 computer shaped like the front of a 1984 desktop machine: the 128×64 LCD sits where the screen would be, the chips sit in the chin, the ISP header sits where the floppy slot was, and a narrower foot runs along the bottom edge.
An agent built it through HeyPCB's MCP server, from one prompt to Claude Code: parts, wiring, outline, placement, routing and checks, all as tool calls. It then wrote the firmware, which draws "hello" on the LCD one pen stroke at a time. KiCad 10 opens the files directly, and the board is on Circuit World to open or fork in HeyPCB (sign-in required).
- AT89S52-24PU (DIP-40) at 11.0592 MHz, running from its own 8 KB of flash (EA tied to VCC).
- 32 KB of SRAM: an AS6C62256 (DIP-28) behind a 74HC573 address latch, mapped at XDATA 0000–7FFF.
- HS12864-15C, a 128×64 ST7920 graphic LCD, in 3-wire serial mode: P1.0 = CS, P1.1 = SID, P1.2 = SCLK, P1.3 = RST. Its backlight runs through R5, 22 Ω.
- USB-C for 5 V only (GCT USB4085), with 5.1 kΩ pull-downs on CC1 and CC2, a 500 mA resettable fuse (Bourns MF-R050) and a power slide switch.
- ISP header (10-pin, USBasp layout) to program the AT89S52, and a 6-pin UART header on P3.0 (RXI) and P3.1 (TXO).
- Reset button, power LED, two M3 holes in the chin.
- 2 layers, ground poured on both. Every part is through-hole except the crystal (an SMD HC-49S): LCSC lists no through-hole 11.0592 MHz part.
Every part has an LCSC number in the BOM.
firmware/ builds with SDCC (4.6.0 here) and the board's ISP header takes the result:
cd firmware
make # build/hello.hex, 2,832 of the AT89S52's 8,192 bytes
make sim # runs the image on a simulated board and renders the screen to build/sim/hello.hex is in the folder already built. The firmware reads ../hello.svg at build time (tools/svg2c.py), fits its 29 Bézier curves to the panel, then traces them with integer maths, stamping a round pen into a frame buffer in the external SRAM and sending the rows under the pen to the LCD after each of its 1,088 steps.
It has run only in simulation. make sim is a cycle-counted 8051 with a model of the ST7920 wired to P1, written from the ST7920 datasheet's serial protocol. Its final screen matches the bitmap computed from hello.svg with 0 pixels different, and SDCC's own simulator (ucsim) agrees on the frame buffer and the cycle count (4,256,702). That check covers the processor and memory, not the LCD model, so how the HS12864-15C itself handles the panel's bottom half is the first thing to confirm on hardware. The screen's colours in the renders are made up; the pixels are exact.
Measured on this revision:
| Check | Result |
|---|---|
| DRC, KiCad 10.0.6 run locally | 0 errors, 0 unconnected; 27 warnings (14 hole-to-hole, 10 silkscreen over copper, 3 silkscreen near the edge) |
| DRC, HeyPCB | 0 errors, 0 unconnected |
| ERC, HeyPCB | 0 errors |
| ERC, KiCad 10.0.6 run locally | 3 errors, all "input pin not driven" on the SRAM's A0–A2 (below) |
| HeyPCB verify | every rung that ran passed; IR drop and the pin-direction check not verified |
| Fab readiness (JLCPCB) | not ready: no blockers, but HeyPCB could only partly confirm the identity of the through-hole resistors and capacitors, so the BOM has no verdict |
Things to know before ordering:
- The 3 KiCad ERC errors are symbol pin types, not wiring. A0–A2 of the SRAM are driven by the 74HC573's outputs, but the 573's LCSC-generated symbol gives its pins no electrical type, so KiCad sees no driver. The same untyped pins are why HeyPCB could not judge the direction of 39 of the 43 signal nets.
- Check the pinouts against the datasheets. The AT89S52, AS6C62256, 74HC573 and HS12864-15C are each wired from a single pin table that no second source confirmed.
- 20 of the 181 plated holes have a 0.150 mm annular ring, under JLCPCB's preferred 0.180 mm (its minimum is 0.13 mm).
- The SRAM is the expensive part: about $17 at LCSC, with 8 in stock when the board was designed. Any 600-mil DIP-28 62256 is pin-compatible.
- The LCD's backlight resistor is a guess. If the module has its own resistor, or the light is too dim or too bright, change R5.
- A few tracks pass near the crystal (advice, not a gate).
| Path | What it is |
|---|---|
hello.kicad_pro, .kicad_sch, .kicad_pcb, .kicad_dru |
The KiCad 10 project |
heypcb-libs/ |
The LCSC parts' symbols and footprints, and one HeyPCB footprint, wired up by fp-lib-table and sym-lib-table |
design.json |
The HeyPCB design the schematic and board are generated from |
fab/ |
Gerbers and drill files, BOM and pick-and-place (CPL) for JLCPCB |
firmware/ |
The SDCC firmware, its simulator, and hello.hex |
hello.svg |
The lettering the firmware draws: one pen stroke |
images/ |
HeyPCB's 3D view and photograph of the board, the schematic, and the simulated screen |
MIT. See LICENSE.