GitHub - EfficientComputer/vtype: Small python-based DSL to generate verilog types · GitHub

This repository was archived by the owner on Sep 13, 2024. It is now read-only.

Name		Name	Last commit message	Last commit date
vtype		vtype
.gitignore		.gitignore
setup.py		setup.py

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Small python-based DSL to generate verilog types

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