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Summary
On this Ryzen 5 5600X, physical CCD 0 is disabled and Linux numbers the surviving CCD 1 as L3 group 0. CoreCycler used that logical index to read CCD 0's core fuse, found no active slots, and disabled per-core Curve Optimizer.
Read the CCD-disable fuses and map Linux's L3 groups to physical CCDs before reading core fuses or encoding CO commands. Keep per-core CO disabled if the active CCD count disagrees with the OS. The register decoding follows
ryzen_smu'sget_fuse_topology, linked in the hardware documentation.Related to #11. This handles a disabled CCD as well as disabled cores within a CCD.
Test plan
test_core_slot_map_matches_the_live_core_disable_fusecontract passes. The installed GUI connects, reads all six offsets, and enables the Curve Optimizer controls. No live CO write test was run.pytest -q -m 'not slow and not contract', 2,908 passed and 2 skipped.beb4d89: four Unix-socket tests blocked by the sandbox and the installed mprime 30.19 failing the verified-version check for 31.4. The socket tests pass outside the sandbox. Both runs report 99.99% total coverage with the same missing line ingui/smu_tab.py; both modified SMU files have 100% coverage.Hardware tested on
Ryzen 5 5600X, ASUS ROG STRIX B550-I GAMING, Omarchy kernel
7.2.5-3-omarchy,ryzen_smu0.1.7. The 5950X case uses simulated fuses.Checklist
ruff check src/andgit diff --checkpass.docs/hardware.mdwith a source reference.AI disclosure: This fix, its tests, and this PR description were produced by AI using GPT 6.1 with xhigh reasoning.