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arm64: dts: ghana: Configure Venice RMI/TSI devs #277

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arm64: dts: ghana: Configure Venice RMI/TSI devs #277

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68 changes: 68 additions & 0 deletions arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-ghana.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -538,6 +538,26 @@
i2c-scl-hz = <1000000>;
mctp-controller;

sbtsi_p0_iod0: sbtsi@0,22400000118 {
reg = <0x0 0x224 0x00000118>;
assigned-address = <0x4c>;
};

sbrmi_p0_iod0: sbrmi@0,22400001118 {
reg = <0x0 0x224 0x00001118>;
assigned-address = <0x3c>;
};

sbtsi_p0_iod0_AB: sbtsi@0,22400000119 {
reg = <0x0 0x224 0x00000119>;
assigned-address = <0x4c>;
};

sbrmi_p0_iod0_AB: sbrmi@0,22400001119 {
reg = <0x0 0x224 0x00001119>;
assigned-address = <0x3c>;
};

scoob_p0: scoob@0,22400002118 {
reg = <0x0 0x224 0x00002118>;
mrl = <69>;
Expand All @@ -559,6 +579,54 @@
i2c-scl-hz = <1000000>;
mctp-controller;

/* TSI Venice A0 2P */
sbtsi_p1_iod0: sbtsi@0,22401000118 {
reg = <0x0 0x224 0x01000118>;
assigned-address = <0x48>;
};

/* RMI Venice A0 2P */
sbrmi_p1_iod0: sbrmi@0,22401001118 {
reg = <0x0 0x224 0x01001118>;
assigned-address = <0x38>;
};

/* TSI Venice A0 2X1P */
sbtsi_2x1p_p1_iod0: sbtsi@0,22400000118 {
reg = <0x0 0x224 0x00000118>;
assigned-address = <0x48>;
};

/* RMI Venice A0 2X1P */
sbrmi_2x1p_p1_iod0: sbrmi@0,22400001118 {
reg = <0x0 0x224 0x00001118>;
assigned-address = <0x38>;
};

/* TSI Venice AB/B0 2P */
sbtsi_p1_iod0_AB: sbtsi@0,22401000119 {
reg = <0x0 0x224 0x01000119>;
assigned-address = <0x48>;
};

/* RMI Venice AB/B0 2P */
sbrmi_p1_iod0_AB: sbrmi@0,22401001119 {
reg = <0x0 0x224 0x01001119>;
assigned-address = <0x38>;
};

/* TSI Venice AB/B0 2x1P */
sbtsi_2x1p_p1_AB_iod0: sbtsi@0,22400000119 {
reg = <0x0 0x224 0x00000119>;
assigned-address = <0x48>;
};

/* RMI Venice AB/B0 2x1P */
sbrmi_2x1p_p1_AB_iod0: sbrmi@0,22400001119 {
reg = <0x0 0x224 0x00001119>;
assigned-address = <0x38>;
};

scoob_2x1p_p1: scoob@0,22400002118 {
reg = <0x0 0x224 0x00002118>;
mrl = <69>;
Expand Down