insn.py: Correcting issue with LR and SC

 * Misunderstanding of spec, had fixed RL and AQ both to 1 for
   LR and SC instructions
 * Now using InstructionAMOType as base class for LR & SC

Author: Peter Birch

riscvmodel/insn.py

@@ -483,16 +483,16 @@ def execute(self, model: Model):
         model.state.intreg[self.rd] = model.state.intreg[self.rs]
 
 
-@isa("lr", RV32A, opcode=0b0101111, funct7=0b0001011, funct3=0b010)
-class InstructionLR(InstructionRType):
+@isa("lr", RV32A, opcode=0b0101111, funct5=0b00010, funct3=0b010)
+class InstructionLR(InstructionAMOType):
     """ Load reserved """
     def execute(self, model: Model):
         # TODO: implement
         pass
 
 
-@isa("sc", RV32A, opcode=0b0101111, funct7=0b0001111, funct3=0b010)
-class InstructionSC(InstructionRType):
+@isa("sc", RV32A, opcode=0b0101111, funct5=0b00011, funct3=0b010)
+class InstructionSC(InstructionAMOType):
     """ Store conditional """
     def execute(self, model: Model):
         # TODO: implement