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system(wba) update STM32WBAxx HAL Drivers to v1.8.0
Included in STM32CubeWBA FW v1.8.0 Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
1 parent 27aca29 commit 4003ada

24 files changed

Lines changed: 464 additions & 260 deletions

‎system/Drivers/STM32WBAxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h‎

Lines changed: 13 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -361,7 +361,10 @@ extern "C" {
361361
#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \
362362
defined(STM32L4S7xx) || defined(STM32L4S9xx)
363363
#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
364-
#endif
364+
#elif defined(STM32L4P5xx) || defined(STM32L4Q5xx)
365+
#define DMA_REQUEST_PSSI DMA_REQUEST_DCMI_PSSI
366+
#define LL_DMAMUX_REQ_PSSI LL_DMAMUX_REQ_DCMI_PSSI
367+
#endif /* STM32L4R5xx || STM32L4R9xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
365368

366369
#endif /* STM32L4 */
367370

@@ -2149,6 +2152,13 @@ extern "C" {
21492152
#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
21502153
#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
21512154

2155+
#if defined(STM32H7RS) || defined(STM32N6)
2156+
#define FMC_SWAPBMAP_DISABLE FMC_SWAPBANK_MODE0
2157+
#define FMC_SWAPBMAP_SDRAM_SRAM FMC_SWAPBANK_MODE1
2158+
#define HAL_SetFMCMemorySwappingConfig HAL_FMC_SetBankSwapConfig
2159+
#define HAL_GetFMCMemorySwappingConfig HAL_FMC_GetBankSwapConfig
2160+
#endif /* STM32H7RS || STM32N6 */
2161+
21522162
/**
21532163
* @}
21542164
*/
@@ -3953,8 +3963,8 @@ extern "C" {
39533963
*/
39543964
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
39553965
defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
3956-
defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || \
3957-
defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3)
3966+
defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || \
3967+
defined (STM32U0) || defined (STM32U3)
39583968
#else
39593969
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
39603970
#endif

‎system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -79,7 +79,7 @@ extern HAL_TickFreqTypeDef uwTickFreq;
7979
* @brief STM32WBAxx HAL Driver version number
8080
*/
8181
#define __STM32WBAxx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */
82-
#define __STM32WBAxx_HAL_VERSION_SUB1 (0x07UL) /*!< [23:16] sub1 version */
82+
#define __STM32WBAxx_HAL_VERSION_SUB1 (0x08UL) /*!< [23:16] sub1 version */
8383
#define __STM32WBAxx_HAL_VERSION_SUB2 (0x00UL) /*!< [15:8] sub2 version */
8484
#define __STM32WBAxx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */
8585
#define __STM32WBAxx_HAL_VERSION ((__STM32WBAxx_HAL_VERSION_MAIN << 24U)\

‎system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_conf_template.h‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -68,7 +68,6 @@ extern "C" {
6868
#define HAL_UART_MODULE_ENABLED
6969
#define HAL_USART_MODULE_ENABLED
7070
#define HAL_WWDG_MODULE_ENABLED
71-
#define HAL_XSPI_MODULE_ENABLED
7271

7372
/* ########################## Oscillator Values adaptation ####################*/
7473
/**
@@ -181,7 +180,6 @@ extern "C" {
181180
#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
182181
#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
183182
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
184-
#define USE_HAL_XSPI_REGISTER_CALLBACKS 0U /* XSPI register callback disabled */
185183

186184
/* ################## SPI peripheral configuration ########################## */
187185

@@ -339,10 +337,6 @@ extern "C" {
339337
#include "stm32wbaxx_hal_wwdg.h"
340338
#endif /* HAL_WWDG_MODULE_ENABLED */
341339

342-
#ifdef HAL_XSPI_MODULE_ENABLED
343-
#include "stm32wbaxx_hal_xspi.h"
344-
#endif /* HAL_XSPI_MODULE_ENABLED */
345-
346340
/* Exported macro ------------------------------------------------------------*/
347341
#ifdef USE_FULL_ASSERT
348342
/**

‎system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gpio_ex.h‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -367,11 +367,11 @@ extern "C" {
367367
/**
368368
* @brief AF 4 selection
369369
*/
370-
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */
371-
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /*!< I2C2 Alternate Function mapping */
372-
#define GPIO_AF4_I2C3 ((uint8_t)0x04) /*!< I2C3 Alternate Function mapping */
373-
#define GPIO_AF4_I2C4 ((uint8_t)0x04) /*!< I2C4 Alternate Function mapping */
374-
#define GPIO_AF4_OTG_HS ((uint8_t)0x04) /*!< OTG-HS Alternate Function mapping */
370+
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */
371+
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /*!< I2C2 Alternate Function mapping */
372+
#define GPIO_AF4_I2C3 ((uint8_t)0x04) /*!< I2C3 Alternate Function mapping */
373+
#define GPIO_AF4_I2C4 ((uint8_t)0x04) /*!< I2C4 Alternate Function mapping */
374+
#define GPIO_AF4_USB_OTG_HS ((uint8_t)0x04) /*!< USB OTG-HS Alternate Function mapping */
375375

376376
/**
377377
* @brief AF 5 selection

‎system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gtzc.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,7 @@ extern "C" {
4343
*/
4444

4545
/*!< Values needed for MPCBB_Attribute_ConfigTypeDef structure sizing */
46-
#if defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) || defined (STM32WBA5Mxx)
46+
#if defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) || defined (STM32WBA5Mxx)
4747
#define GTZC_MPCBB_NB_VCTR_REG_MAX 4U /*!< Maximum number of superblocks */
4848
#elif defined (STM32WBA62xx) || defined (STM32WBA63xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) || defined (STM32WBA6Mxx)
4949
#define GTZC_MPCBB_NB_VCTR_REG_MAX 28U /*!< Maximum number of superblocks */

‎system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_hash.h‎

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -291,11 +291,13 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef *hhash); /*!< pointer
291291
* @arg @ref HASH_FLAG_DMAS DMA interface is enabled (DMAE=1) or a transfer is ongoing.
292292
* @arg @ref HASH_FLAG_BUSY The hash core is Busy : processing a block of data.
293293
* @arg @ref HASH_FLAG_DINNE DIN not empty : the input buffer contains at least one word of data.
294-
* @retval The new state of __FLAG__ (TRUE or FALSE).
294+
* @retval The new state of __FLAG__ (SET or RESET).
295295
*/
296-
#define __HAL_HASH_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) > 8U) ? \
297-
(((__HANDLE__)->Instance->CR & (__FLAG__)) == (__FLAG__)) :\
298-
(((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) )
296+
#define __HAL_HASH_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) > 8U) ? \
297+
((((__HANDLE__)->Instance->CR & (__FLAG__)) == \
298+
(__FLAG__)) ? SET : RESET) : \
299+
((((__HANDLE__)->Instance->SR & (__FLAG__)) == \
300+
(__FLAG__)) ? SET : RESET) )
299301

300302
/** @brief Clear the specified HASH flag.
301303
* @param __HANDLE__ specifies the HASH handle.
@@ -389,7 +391,7 @@ HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);
389391
void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
390392
void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
391393
HAL_StatusTypeDef HAL_HASH_GetConfig(HASH_HandleTypeDef *hhash, HASH_ConfigTypeDef *pConf);
392-
HAL_StatusTypeDef HAL_HASH_SetConfig(HASH_HandleTypeDef *hhash, HASH_ConfigTypeDef *pConf);
394+
HAL_StatusTypeDef HAL_HASH_SetConfig(HASH_HandleTypeDef *hhash, const HASH_ConfigTypeDef *pConf);
393395

394396
/* Callbacks Register/UnRegister functions ***********************************/
395397
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)

‎system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_i2c_ex.h‎

Lines changed: 49 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -105,6 +105,7 @@ typedef struct
105105
#define I2C_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3 */
106106

107107
#if defined(I2C_TRIG_GRP1)
108+
#if defined(GPDMA1)
108109
#define I2C_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x00000000U))
109110
/*!< HW Trigger signal is GPDMA_CH0_TRG */
110111
#define I2C_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x1UL << I2C_AUTOCR_TRIGSEL_Pos))
@@ -113,6 +114,17 @@ typedef struct
113114
/*!< HW Trigger signal is GPDMA_CH2_TRG */
114115
#define I2C_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x3UL << I2C_AUTOCR_TRIGSEL_Pos))
115116
/*!< HW Trigger signal is GPDMA_CH3_TRG */
117+
#endif /* GPDMA1 */
118+
#if defined(LPDMA1)
119+
#define I2C_GRP1_LPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x00000000U))
120+
/*!< HW Trigger signal is LPDMA_CH0_TRG */
121+
#define I2C_GRP1_LPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x1UL << I2C_AUTOCR_TRIGSEL_Pos))
122+
/*!< HW Trigger signal is LPDMA_CH1_TRG */
123+
#define I2C_GRP1_LPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x2UL << I2C_AUTOCR_TRIGSEL_Pos))
124+
/*!< HW Trigger signal is LPDMA_CH2_TRG */
125+
#define I2C_GRP1_LPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x3UL << I2C_AUTOCR_TRIGSEL_Pos))
126+
/*!< HW Trigger signal is LPDMA_CH3_TRG */
127+
#endif /* LPDMA1 */
116128
#define I2C_GRP1_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x4UL << I2C_AUTOCR_TRIGSEL_Pos))
117129
/*!< HW Trigger signal is EXTI5_TRG */
118130
#define I2C_GRP1_EXTI9_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x5UL << I2C_AUTOCR_TRIGSEL_Pos))
@@ -135,6 +147,7 @@ typedef struct
135147
/*!< HW Trigger signal is RTC_WUT_TRG */
136148
#endif /* I2C_TRIG_GRP1 */
137149

150+
#if defined(GPDMA1)
138151
#define I2C_GRP2_GPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x00000000U))
139152
/*!< HW Trigger signal is GPDMA_CH0_TRG */
140153
#define I2C_GRP2_GPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x1UL << I2C_AUTOCR_TRIGSEL_Pos))
@@ -143,6 +156,17 @@ typedef struct
143156
/*!< HW Trigger signal is GPDMA_CH2_TRG */
144157
#define I2C_GRP2_GPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x3UL << I2C_AUTOCR_TRIGSEL_Pos))
145158
/*!< HW Trigger signal is GPDMA_CH3_TRG */
159+
#endif /* GPDMA1 */
160+
#if defined(LPDMA1)
161+
#define I2C_GRP2_LPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x00000000U))
162+
/*!< HW Trigger signal is LPDMA_CH0_TRG */
163+
#define I2C_GRP2_LPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x1UL << I2C_AUTOCR_TRIGSEL_Pos))
164+
/*!< HW Trigger signal is LPDMA_CH1_TRG */
165+
#define I2C_GRP2_LPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x2UL << I2C_AUTOCR_TRIGSEL_Pos))
166+
/*!< HW Trigger signal is LPDMA_CH2_TRG */
167+
#define I2C_GRP2_LPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x3UL << I2C_AUTOCR_TRIGSEL_Pos))
168+
/*!< HW Trigger signal is LPDMA_CH3_TRG */
169+
#endif /* LPDMA1 */
146170
#define I2C_GRP2_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x4UL << I2C_AUTOCR_TRIGSEL_Pos))
147171
/*!< HW Trigger signal is EXTI5_TRG */
148172
#define I2C_GRP2_EXTI8_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x5UL << I2C_AUTOCR_TRIGSEL_Pos))
@@ -297,6 +321,7 @@ HAL_StatusTypeDef HAL_I2CEx_ClearConfigAutonomousMode(I2C_HandleTypeDef *hi2c);
297321

298322
#else
299323

324+
#if defined(GPDMA1)
300325
#define IS_I2C_GRP1_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == I2C_GRP1_GPDMA_CH0_TCF_TRG ) || \
301326
((__SOURCE__) == I2C_GRP1_GPDMA_CH1_TCF_TRG ) || \
302327
((__SOURCE__) == I2C_GRP1_GPDMA_CH2_TCF_TRG ) || \
@@ -317,6 +342,30 @@ HAL_StatusTypeDef HAL_I2CEx_ClearConfigAutonomousMode(I2C_HandleTypeDef *hi2c);
317342
((__SOURCE__) == I2C_GRP2_LPTIM1_CH1_TRG ) || \
318343
((__SOURCE__) == I2C_GRP2_RTC_ALRA_TRG ) || \
319344
((__SOURCE__) == I2C_GRP2_RTC_WUT_TRG ))
345+
#endif /* GPDMA1 */
346+
347+
#if defined(LPDMA1)
348+
#define IS_I2C_GRP1_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == I2C_GRP1_LPDMA_CH0_TCF_TRG ) || \
349+
((__SOURCE__) == I2C_GRP1_LPDMA_CH1_TCF_TRG ) || \
350+
((__SOURCE__) == I2C_GRP1_LPDMA_CH2_TCF_TRG ) || \
351+
((__SOURCE__) == I2C_GRP1_LPDMA_CH3_TCF_TRG ) || \
352+
((__SOURCE__) == I2C_GRP1_EXTI5_TRG ) || \
353+
((__SOURCE__) == I2C_GRP1_EXTI9_TRG ) || \
354+
((__SOURCE__) == I2C_GRP1_LPTIM1_CH1_TRG ) || \
355+
((__SOURCE__) == I2C_GRP1_LPTIM2_CH1_TRG ) || \
356+
((__SOURCE__) == I2C_GRP1_RTC_ALRA_TRG ) || \
357+
((__SOURCE__) == I2C_GRP1_RTC_WUT_TRG ))
358+
359+
#define IS_I2C_GRP2_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == I2C_GRP2_LPDMA_CH0_TCF_TRG ) || \
360+
((__SOURCE__) == I2C_GRP2_LPDMA_CH1_TCF_TRG ) || \
361+
((__SOURCE__) == I2C_GRP2_LPDMA_CH2_TCF_TRG ) || \
362+
((__SOURCE__) == I2C_GRP2_LPDMA_CH3_TCF_TRG ) || \
363+
((__SOURCE__) == I2C_GRP2_EXTI5_TRG ) || \
364+
((__SOURCE__) == I2C_GRP2_EXTI8_TRG ) || \
365+
((__SOURCE__) == I2C_GRP2_LPTIM1_CH1_TRG ) || \
366+
((__SOURCE__) == I2C_GRP2_RTC_ALRA_TRG ) || \
367+
((__SOURCE__) == I2C_GRP2_RTC_WUT_TRG ))
368+
#endif /* LPDMA1 */
320369
#endif /* COMP1 && COMP2 */
321370

322371
#if defined(I2C_TRIG_GRP1)

‎system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pwr_ex.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -73,8 +73,11 @@ extern "C" {
7373
#define PWR_SRAM2_FULL_STOP_RETENTION PWR_CR2_SRAM2PDS1 /*!< SRAM2 full retention in Stop modes */
7474
#endif /* !defined(PWR_STOP3_SUPPORT) */
7575

76+
#if defined (PWR_CR2_ICRAMPDS)
7677
/* Cache RAMs retention defines */
7778
#define PWR_ICACHE_FULL_STOP_RETENTION PWR_CR2_ICRAMPDS /*!< ICACHE SRAM retention in Stop modes */
79+
#endif /* PWR_CR2_ICRAMPDS */
80+
7881
#if defined(PWR_STOP2_SUPPORT)
7982
#if defined(USB_OTG_HS)
8083
/* USB_OTG_HS SRAM power-down in Stop modes */

‎system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rtc_ex.h‎

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -854,12 +854,20 @@ typedef struct
854854
* @{
855855
*/
856856
#define TAMP_DEVICESECRETS_ERASE_NONE 0U /*! < No Erase */
857+
#ifdef TAMP_RPCFGR_RPCFG
857858
#define TAMP_DEVICESECRETS_ERASE_SRAM2 TAMP_RPCFGR_RPCFG_1 /*!< SRAM2 */
858859
#define TAMP_DEVICESECRETS_ERASE_RHUK TAMP_RPCFGR_RPCFG_2 /*!< RHUK */
859860
#define TAMP_DEVICESECRETS_ERASE_ICACHE TAMP_RPCFGR_RPCFG_3 /*!< ICACHE */
860861
#define TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH TAMP_RPCFGR_RPCFG_4 /*!< SAES, AES and HASH */
861862
#define TAMP_DEVICESECRETS_ERASE_PKA_SRAM TAMP_RPCFGR_RPCFG_5 /*!< Initialization */
862863
#define TAMP_DEVICESECRETS_ERASE_ALL TAMP_RPCFGR_RPCFG /*!< All */
864+
#elif defined(TAMP_ERCFGR_ERCFG)
865+
#define TAMP_DEVICESECRETS_ERASE_SRAM2 TAMP_ERCFGR_ERCFG_1 /*!< SRAM2 */
866+
#define TAMP_DEVICESECRETS_ERASE_ICACHE TAMP_ERCFGR_ERCFG_3 /*!< ICACHE */
867+
#define TAMP_DEVICESECRETS_ERASE_AES_HASH_OTFDEC TAMP_ERCFGR_ERCFG_4 /*!< AES, HASH and OTFDEC */
868+
#define TAMP_DEVICESECRETS_ERASE_PKA_SRAM TAMP_ERCFGR_ERCFG_5 /*!< PKA SRAM */
869+
#define TAMP_DEVICESECRETS_ERASE_ALL TAMP_ERCFGR_ERCFG /*!< All */
870+
#endif
863871
/**
864872
* @}
865873
*/
@@ -1609,7 +1617,7 @@ uint32_t HAL_RTCEx_BKUPRead(const RTC_HandleTypeDef *hrtc, uint32_t Bac
16091617
void HAL_RTCEx_BKUPErase(const RTC_HandleTypeDef *hrtc);
16101618
void HAL_RTCEx_BKUPBlock(const RTC_HandleTypeDef *hrtc);
16111619
void HAL_RTCEx_BKUPUnblock(const RTC_HandleTypeDef *hrtc);
1612-
#ifdef TAMP_RPCFGR_RPCFG
1620+
#if defined (TAMP_RPCFGR_RPCFG) || defined(TAMP_ERCFGR_ERCFG)
16131621
void HAL_RTCEx_ConfigEraseDeviceSecrets(const RTC_HandleTypeDef *hrtc, uint32_t DeviceSecretConf);
16141622
#endif /* TAMP_RPCFGR_RPCFG */
16151623
/**

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