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system(h5) update STM32H5xx HAL Drivers to v1.6.0
Included in STM32CubeH5 FW v1.6.0 Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
1 parent 734f525 commit 3f0f311

137 files changed

Lines changed: 50721 additions & 2242 deletions

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‎system/Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h‎

Lines changed: 19 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -361,7 +361,9 @@ extern "C" {
361361
#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \
362362
defined(STM32L4S7xx) || defined(STM32L4S9xx)
363363
#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
364-
#endif
364+
#elif defined(STM32L4P5xx) || defined(STM32L4Q5xx)
365+
#define DMA_REQUEST_PSSI DMA_REQUEST_DCMI_PSSI
366+
#endif /* STM32L4R5xx || STM32L4R9xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
365367

366368
#endif /* STM32L4 */
367369

@@ -564,6 +566,9 @@ extern "C" {
564566
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
565567
#define OB_nBOOT0_SET OB_NBOOT0_SET
566568
#endif /* STM32U0 */
569+
#if defined(STM32H5)
570+
#define FLASH_ECC_AREA_EDATA FLASH_ECC_AREA_EDATA_BANK1
571+
#endif /* STM32H5 */
567572

568573
/**
569574
* @}
@@ -2025,6 +2030,9 @@ extern "C" {
20252030

20262031
#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK
20272032
#endif
2033+
#if defined (STM32H7RS)
2034+
#define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO PWR_SMPS_1V8_SUPPLIES_EXT_VDD_SUPPLIES_LDO
2035+
#endif
20282036

20292037
/**
20302038
* @}
@@ -2146,6 +2154,13 @@ extern "C" {
21462154
#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
21472155
#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
21482156

2157+
#if defined(STM32H7RS) || defined(STM32N6)
2158+
#define FMC_SWAPBMAP_DISABLE FMC_SWAPBANK_MODE0
2159+
#define FMC_SWAPBMAP_SDRAM_SRAM FMC_SWAPBANK_MODE1
2160+
#define HAL_SetFMCMemorySwappingConfig HAL_FMC_SetBankSwapConfig
2161+
#define HAL_GetFMCMemorySwappingConfig HAL_FMC_GetBankSwapConfig
2162+
#endif /* STM32H7RS || STM32N6 */
2163+
21492164
/**
21502165
* @}
21512166
*/
@@ -3699,8 +3714,7 @@ extern "C" {
36993714
#endif
37003715

37013716
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
3702-
defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || \
3703-
defined(STM32U0)
3717+
defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0)
37043718
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
37053719
#else
37063720
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3951,8 +3965,8 @@ extern "C" {
39513965
*/
39523966
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
39533967
defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
3954-
defined (STM32WBA) || defined (STM32H5) || \
3955-
defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3)
3968+
defined (STM32U3) || defined (STM32WBA) || defined (STM32H5) || defined (STM32U0) || \
3969+
defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS)
39563970
#else
39573971
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
39583972
#endif

‎system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h‎

Lines changed: 71 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -157,6 +157,7 @@ extern HAL_TickFreqTypeDef uwTickFreq;
157157
#define IS_SBS_ETHERNET_CONFIG(CONFIG) (((CONFIG) == SBS_ETH_MII) || \
158158
((CONFIG) == SBS_ETH_RMII))
159159

160+
160161
/**
161162
* @}
162163
*/
@@ -293,6 +294,54 @@ extern HAL_TickFreqTypeDef uwTickFreq;
293294
* @}
294295
*/
295296

297+
#if defined(SBS_OTGHSPHYTUNER2_TXPREEMPAMPTUNE)
298+
/** @defgroup SBS_OTG_PHYTUNER_PreemphasisCurrent OTG PHYTUNER Preemphasis Current
299+
* @{
300+
*/
301+
302+
/** @brief High-speed (HS) transmitter preemphasis current control
303+
*/
304+
#define SBS_OTG_HS_PHY_PREEMP_DISABLED 0x00000000U /*!< HS transmitter preemphasis circuit disabled */
305+
#define SBS_OTG_HS_PHY_PREEMP_1X SBS_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 /*!< HS transmitter preemphasis circuit sources 1x preemphasis current */
306+
#define SBS_OTG_HS_PHY_PREEMP_2X SBS_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1 /*!< HS transmitter preemphasis circuit sources 2x preemphasis current */
307+
#define SBS_OTG_HS_PHY_PREEMP_3X (SBS_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 | SBS_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1) /*!< HS transmitter preemphasis circuit sources 3x preemphasis current */
308+
309+
/**
310+
* @}
311+
*/
312+
#endif /* SBS_OTGHSPHYTUNER2_TXPREEMPAMPTUNE */
313+
314+
#if defined(SBS_OTGHSPHYTUNER2_SQRXTUNE)
315+
/** @defgroup SBS_OTG_PHYTUNER_SquelchThreshold OTG PHYTUNER Squelch Threshold
316+
* @{
317+
*/
318+
319+
/** @brief Squelch threshold adjustment
320+
*/
321+
#define SBS_OTG_HS_PHY_SQUELCH_15PERCENT 0x00000000U /*!< +15% (recommended value) */
322+
#define SBS_OTG_HS_PHY_SQUELCH_0PERCENT (SBS_OTGHSPHYTUNER2_SQRXTUNE_0 | SBS_OTGHSPHYTUNER2_SQRXTUNE_1) /*!< 0% (default value) */
323+
324+
/**
325+
* @}
326+
*/
327+
#endif /* SBS_OTGHSPHYTUNER2_SQRXTUNE */
328+
329+
#if defined(SBS_OTGHSPHYTUNER2_COMPDISTUNE)
330+
/** @defgroup SBS_OTG_PHYTUNER_DisconnectThreshold OTG PHYTUNER Disconnect Threshold
331+
* @{
332+
*/
333+
334+
/** @brief Disconnect threshold adjustment
335+
*/
336+
#define SBS_OTG_HS_PHY_DISCONNECT_5_9PERCENT SBS_OTGHSPHYTUNER2_COMPDISTUNE_1 /*!< +5.9% (recommended value) */
337+
#define SBS_OTG_HS_PHY_DISCONNECT_0PERCENT SBS_OTGHSPHYTUNER2_COMPDISTUNE_0 /*!< 0% (default value) */
338+
339+
/**
340+
* @}
341+
*/
342+
343+
#endif /* SBS_OTGHSPHYTUNER2_COMPDISTUNE */
344+
296345
/**
297346
* @}
298347
*/
@@ -710,6 +759,22 @@ extern HAL_TickFreqTypeDef uwTickFreq;
710759
#define IS_SBS_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == SBS_SEC) ||\
711760
((__ATTRIBUTES__) == SBS_NSEC))
712761

762+
#if defined(SBS_OTGHSPHYTUNER2_COMPDISTUNE)
763+
#define IS_SBS_OTGPHY_DISCONNECT(__VALUE__) (((__VALUE__) == SBS_OTG_HS_PHY_DISCONNECT_5_9PERCENT) || \
764+
((__VALUE__) == SBS_OTG_HS_PHY_DISCONNECT_0PERCENT))
765+
#endif /* SBS_OTGHSPHYTUNER2_COMPDISTUNE*/
766+
#if defined(SBS_OTGHSPHYTUNER2_SQRXTUNE)
767+
#define IS_SBS_OTGPHY_SQUELCH(__VALUE__) (((__VALUE__) == SBS_OTG_HS_PHY_SQUELCH_0PERCENT) || \
768+
((__VALUE__) == SBS_OTG_HS_PHY_SQUELCH_15PERCENT))
769+
#endif /* SBS_OTGHSPHYTUNER2_SQRXTUNE */
770+
771+
#if defined(SBS_OTGHSPHYTUNER2_TXPREEMPAMPTUNE)
772+
#define IS_SBS_OTGPHY_PREEMPHASIS(__VALUE__) (((__VALUE__) == SBS_OTG_HS_PHY_PREEMP_DISABLED) || \
773+
((__VALUE__) == SBS_OTG_HS_PHY_PREEMP_1X) || \
774+
((__VALUE__) == SBS_OTG_HS_PHY_PREEMP_2X) || \
775+
((__VALUE__) == SBS_OTG_HS_PHY_PREEMP_3X))
776+
#endif /* SBS_OTGHSPHYTUNER2_TXPREEMPAMPTUNE */
777+
713778
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
714779

715780
#define IS_SBS_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SBS_MPU_NSEC) == SBS_MPU_NSEC) || \
@@ -839,6 +904,12 @@ uint32_t HAL_SBS_GetPMOSVddIO2CompensationValue(void);
839904
void HAL_SBS_FLASH_EnableECCNMI(void);
840905
void HAL_SBS_FLASH_DisableECCNMI(void);
841906
uint32_t HAL_SBS_FLASH_ECCNMI_IsDisabled(void);
907+
void HAL_SBS_SetOTGPHYDisconnectThreshold(uint32_t DisconnectThreshold);
908+
uint32_t HAL_SBS_GetOTGPHYDisconnectThreshold(void);
909+
void HAL_SBS_SetOTGPHYSquelchThreshold(uint32_t SquelchThreshold);
910+
uint32_t HAL_SBS_GetOTGPHYSquelchThreshold(void);
911+
void HAL_SBS_SetOTGPHYPreemphasisCurrent(uint32_t PreemphasisCurrent);
912+
uint32_t HAL_SBS_GetOTGPHYPreemphasisCurrent(void);
842913

843914
/**
844915
* @}

‎system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc.h‎

Lines changed: 78 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -204,6 +204,10 @@ typedef struct
204204
uint32_t SamplingMode; /*!< Select the sampling mode to be used for ADC group regular conversion.
205205
This parameter can be a value of @ref ADC_regular_sampling_mode */
206206

207+
#if defined(ADC3)
208+
uint32_t ConversionDataManagement; /*!< Specifies whether the Data conversion data is managed: using the DMA (one shot
209+
or circular),or stored in the DR register or transferred to ADF register.*/
210+
#endif /* ADC3 */
207211
FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA
208212
transfer stops when number of conversions is reached) or in continuous
209213
mode (DMA transfer unlimited, whatever number of conversions).
@@ -664,7 +668,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
664668

665669
/* Triggers specific to some devices of STM32H5 series */
666670
#if defined(TIM8)
667-
/* Devices STM32H563/H573xx */
671+
/* Devices STM32H563/H573xx and STM32H5Ex/H5Fxxx */
668672
#define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion
669673
trigger from external peripheral: TIM4 channel 4 event (capture compare).
670674
Specific to devices STM32H563/H573xx. */
@@ -680,6 +684,12 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
680684
#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion
681685
trigger from external peripheral: TIM15 TRGO event.
682686
Specific to devices STM32H563/H573xx. */
687+
#if defined(ADC3)
688+
/* Devices STM32H5Ex/H5Fxxx */
689+
#define ADC_EXTERNALTRIG_PLAY_OUT7 (LL_ADC_REG_TRIG_EXT_PLAY_OUT7) /*!< ADC group regular conversion
690+
trigger from external peripheral: PLAY_OUT7 event.
691+
Specific to devices STM32H5Ex/H5Fxxx. */
692+
#endif /* ADC3 */
683693
#else
684694
/* Devices STM32H503xx */
685695
#define ADC_EXTERNALTRIG_T7_TRGO (LL_ADC_REG_TRIG_EXT_TIM7_TRGO) /*!< ADC group regular conversion
@@ -809,18 +819,43 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
809819
#define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< External channel (GPIO pin) ADCx_IN18 */
810820
#define ADC_CHANNEL_19 (LL_ADC_CHANNEL_19) /*!< External channel (GPIO pin) ADCx_IN19 */
811821
#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< Internal channel VrefInt: Internal
812-
voltage reference, channel specific to ADC1. */
822+
voltage reference, channel specific to ADC1, ADC3. */
813823
#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< Internal channel Temperature sensor,
814-
channel specific to ADC1. */
824+
channel specific to ADC1, ADC3. */
815825
#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< Internal channel Vbat/4: Vbat voltage
816826
through a divider ladder of factor 1/4 to have channel voltage always below
817827
Vdda, channel specific to ADC2. */
818828
#define ADC_CHANNEL_VDDCORE (LL_ADC_CHANNEL_VDDCORE) /*!< Internal channel Vddcore, channel
819829
specific to ADC2. */
830+
#if defined(ADC3)
831+
#define ADC_CHANNEL_VBAT_ADC3 (LL_ADC_CHANNEL_VBAT_ADC3) /*!< Internal channel Vbat/4: Vbat voltage
832+
through a divider ladder of factor 1/4 to have channel voltage always below
833+
Vdda, channel specific to ADC3. */
834+
#define ADC_CHANNEL_VDDCORE_ADC3 (LL_ADC_CHANNEL_VDDCORE_ADC3) /*!< Internal channel Vddcore, channel
835+
specific to ADC3. */
836+
#define ADC_CHANNEL_DAC1_CH1 (LL_ADC_CHANNEL_DAC1_CH1) /*!< Internal channel DAC1 channel 1,
837+
channel specific to ADC3 */
838+
#define ADC_CHANNEL_DAC1_CH2 (LL_ADC_CHANNEL_DAC1_CH2) /*!< Internal channel DAC1 channel 2,
839+
channel specific to ADC3 */
840+
#endif /* ADC3 */
820841
/**
821842
* @}
822843
*/
823844

845+
#if defined(ADC3)
846+
/** @defgroup ADC_ConversionDataManagement ADC Conversion Data Management
847+
* @{
848+
*/
849+
#define ADC_CONVERSIONDATA_DR (0x00000000UL) /*!< Regular Conversion data stored in DR register
850+
only */
851+
#if defined(ADC_CFGR_ADFCFG)
852+
#define ADC_CONVERSIONDATA_MDF (ADC_CFGR_ADFCFG) /*!< MDF (ADF) mode selected */
853+
#endif /* ADC_CFGR_ADFCFG */
854+
/**
855+
* @}
856+
*/
857+
858+
#endif /* ADC3*/
824859
/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - ADC analog watchdog (AWD) number
825860
* @{
826861
*/
@@ -1007,6 +1042,22 @@ out-of-window sample to raise flag or interrupt */
10071042
*/
10081043
/* Macro reserved for internal HAL driver usage, not intended to be used in */
10091044
/* code of final user. */
1045+
#if defined(ADC3)
1046+
/**
1047+
* @brief Verify the ADC data conversion setting.
1048+
* @param DATA : programmed DATA conversion mode.
1049+
* @retval SET (DATA is a valid value) or RESET (DATA is invalid)
1050+
*/
1051+
#if defined(ADC_CFGR_ADFCFG)
1052+
#define IS_ADC_CONVERSIONDATAMGT(DATA) \
1053+
((((DATA) == ADC_CONVERSIONDATA_DR)) || \
1054+
(((DATA) == ADC_CONVERSIONDATA_MDF)))
1055+
#else
1056+
#define IS_ADC_CONVERSIONDATAMGT(DATA) \
1057+
(((DATA) == ADC_CONVERSIONDATA_DR))
1058+
1059+
#endif /* ADC_CFGR_ADFCFG */
1060+
#endif /* ADC3*/
10101061

10111062
/**
10121063
* @brief Return resolution bits in CFGR register RES[1:0] field.
@@ -1129,7 +1180,7 @@ out-of-window sample to raise flag or interrupt */
11291180
* @param __REGTRIG__ programmed ADC regular conversions external trigger.
11301181
* @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid)
11311182
*/
1132-
#if defined(TIM8)
1183+
#if defined(TIM8) && !defined(ADC3)
11331184
/* Devices STM32H563/H573xx */
11341185
#define IS_ADC_EXTTRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
11351186
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
@@ -1151,6 +1202,29 @@ out-of-window sample to raise flag or interrupt */
11511202
((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM1_CH1) || \
11521203
((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM2_CH1) || \
11531204
((__REGTRIG__) == ADC_SOFTWARE_START) )
1205+
#elif defined(ADC3)
1206+
/* Devices STM32H5Ex/H5Fxxx */
1207+
#define IS_ADC_EXTTRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
1208+
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
1209+
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
1210+
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \
1211+
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \
1212+
((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \
1213+
((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \
1214+
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \
1215+
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
1216+
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
1217+
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
1218+
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
1219+
((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \
1220+
((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
1221+
((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
1222+
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
1223+
((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT15) || \
1224+
((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM1_CH1) || \
1225+
((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM2_CH1) || \
1226+
((__REGTRIG__) == ADC_EXTERNALTRIG_PLAY_OUT7) || \
1227+
((__REGTRIG__) == ADC_SOFTWARE_START) )
11541228
#else
11551229
/* Devices STM32H503xx */
11561230
#define IS_ADC_EXTTRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \

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