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system(wba): update STM32WBAxx CMSIS Drivers to v1.9.0
Included in STM32CubeWBA FW v1.9.0 Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
1 parent ca4a07c commit 05aa8eb

103 files changed

Lines changed: 43000 additions & 155 deletions

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‎system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/Templates/partition_stm32wba23xx.h‎

Lines changed: 579 additions & 0 deletions
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‎system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/Templates/partition_stm32wba25xx.h‎

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‎system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/partition_stm32wbaxx.h‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,11 @@
4242
* @{
4343
*/
4444

45-
#if defined(STM32WBA52xx)
45+
#if defined(STM32WBA23xx)
46+
#include "partition_stm32wba23xx.h"
47+
#elif defined(STM32WBA25xx)
48+
#include "partition_stm32wba25xx.h"
49+
#elif defined(STM32WBA52xx)
4650
#include "partition_stm32wba52xx.h"
4751
#elif defined(STM32WBA54xx)
4852
#include "partition_stm32wba54xx.h"

‎system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba20xx.h‎

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‎system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba23xx.h‎

Lines changed: 13359 additions & 0 deletions
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‎system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba25xx.h‎

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‎system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba50xx.h‎

Lines changed: 23 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -620,7 +620,7 @@ typedef struct
620620
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
621621
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
622622
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
623-
uint32_t RESERVED;
623+
__IO uint32_t NSCR; /*!< RNG noise source control register, Address offset: 0x0C */
624624
__IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */
625625
} RNG_TypeDef;
626626

@@ -6695,15 +6695,36 @@ typedef struct
66956695
#define RNG_DR_RNDATA_Msk (0xFFFFFFFFUL << RNG_DR_RNDATA_Pos) /*!< 0xFFFFFFFF */
66966696
#define RNG_DR_RNDATA RNG_DR_RNDATA_Msk
66976697

6698+
/******************** Bit definition for RNG_NSCR register ********************/
6699+
#define RNG_NSCR_EN_OSC1_Pos (0UL)
6700+
#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */
6701+
#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk /*!< EN_OSC1[2:0] bits (Each bit drives one oscillator enable signal input of instance number 1, gated with RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.) */
6702+
#define RNG_NSCR_EN_OSC2_Pos (3UL)
6703+
#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */
6704+
#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk /*!< EN_OSC2[2:0] bits (Each bit drives one oscillator enable signal input of instance number 2, gated with RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.) */
6705+
#define RNG_NSCR_EN_OSC3_Pos (6UL)
6706+
#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */
6707+
#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk /*!< EN_OSC3[2:0] bits (Each bit drives one oscillator enable signal input of instance number 3, gated with RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.) */
6708+
#define RNG_NSCR_EN_OSC4_Pos (9UL)
6709+
#define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */
6710+
#define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk /*!< EN_OSC4[2:0] bits (Each bit drives one oscillator enable signal input of instance number 1, gated with RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.) */
6711+
#define RNG_NSCR_EN_OSC5_Pos (12UL)
6712+
#define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */
6713+
#define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk /*!< EN_OSC5[2:0] bits (Each bit drives one oscillator enable signal input of instance number 2, gated with RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.) */
6714+
#define RNG_NSCR_EN_OSC6_Pos (15UL)
6715+
#define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */
6716+
#define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk /*!< EN_OSC6[2:0] bits (Each bit drives one oscillator enable signal input of instance number 3, gated with RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.) */
6717+
66986718
/******************** Bits definition for RNG_HTCR register *******************/
66996719
#define RNG_HTCR_HTCFG_Pos (0UL)
67006720
#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */
67016721
#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk
6722+
67026723
/******************** RNG Nist Compliance Values *******************/
67036724
#define RNG_CR_NIST_VALUE (0x00F02D00U)
6725+
#define RNG_NSCR_NIST_VALUE (0x0003FFFFU)
67046726
#define RNG_HTCR_NIST_VALUE (0xAAC7U)
67056727

6706-
67076728
/******************************************************************************/
67086729
/* */
67096730
/* Real-Time Clock (RTC) */

‎system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba52xx.h‎

Lines changed: 23 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -713,7 +713,7 @@ typedef struct
713713
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
714714
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
715715
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
716-
uint32_t RESERVED;
716+
__IO uint32_t NSCR; /*!< RNG noise source control register, Address offset: 0x0C */
717717
__IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */
718718
} RNG_TypeDef;
719719

@@ -10597,15 +10597,36 @@ typedef struct
1059710597
#define RNG_DR_RNDATA_Msk (0xFFFFFFFFUL << RNG_DR_RNDATA_Pos) /*!< 0xFFFFFFFF */
1059810598
#define RNG_DR_RNDATA RNG_DR_RNDATA_Msk
1059910599

10600+
/******************** Bit definition for RNG_NSCR register ********************/
10601+
#define RNG_NSCR_EN_OSC1_Pos (0UL)
10602+
#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */
10603+
#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk /*!< EN_OSC1[2:0] bits (Each bit drives one oscillator enable signal input of instance number 1, gated with RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.) */
10604+
#define RNG_NSCR_EN_OSC2_Pos (3UL)
10605+
#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */
10606+
#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk /*!< EN_OSC2[2:0] bits (Each bit drives one oscillator enable signal input of instance number 2, gated with RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.) */
10607+
#define RNG_NSCR_EN_OSC3_Pos (6UL)
10608+
#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */
10609+
#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk /*!< EN_OSC3[2:0] bits (Each bit drives one oscillator enable signal input of instance number 3, gated with RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.) */
10610+
#define RNG_NSCR_EN_OSC4_Pos (9UL)
10611+
#define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */
10612+
#define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk /*!< EN_OSC4[2:0] bits (Each bit drives one oscillator enable signal input of instance number 1, gated with RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.) */
10613+
#define RNG_NSCR_EN_OSC5_Pos (12UL)
10614+
#define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */
10615+
#define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk /*!< EN_OSC5[2:0] bits (Each bit drives one oscillator enable signal input of instance number 2, gated with RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.) */
10616+
#define RNG_NSCR_EN_OSC6_Pos (15UL)
10617+
#define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */
10618+
#define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk /*!< EN_OSC6[2:0] bits (Each bit drives one oscillator enable signal input of instance number 3, gated with RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.) */
10619+
1060010620
/******************** Bits definition for RNG_HTCR register *******************/
1060110621
#define RNG_HTCR_HTCFG_Pos (0UL)
1060210622
#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */
1060310623
#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk
10624+
1060410625
/******************** RNG Nist Compliance Values *******************/
1060510626
#define RNG_CR_NIST_VALUE (0x00F02D00U)
10627+
#define RNG_NSCR_NIST_VALUE (0x0003FFFFU)
1060610628
#define RNG_HTCR_NIST_VALUE (0xAAC7U)
1060710629

10608-
1060910630
/******************************************************************************/
1061010631
/* */
1061110632
/* Real-Time Clock (RTC) */

‎system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba54xx.h‎

Lines changed: 23 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -752,7 +752,7 @@ typedef struct
752752
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
753753
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
754754
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
755-
uint32_t RESERVED;
755+
__IO uint32_t NSCR; /*!< RNG noise source control register, Address offset: 0x0C */
756756
__IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */
757757
} RNG_TypeDef;
758758

@@ -10960,15 +10960,36 @@ typedef struct
1096010960
#define RNG_DR_RNDATA_Msk (0xFFFFFFFFUL << RNG_DR_RNDATA_Pos) /*!< 0xFFFFFFFF */
1096110961
#define RNG_DR_RNDATA RNG_DR_RNDATA_Msk
1096210962

10963+
/******************** Bit definition for RNG_NSCR register ********************/
10964+
#define RNG_NSCR_EN_OSC1_Pos (0UL)
10965+
#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */
10966+
#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk /*!< EN_OSC1[2:0] bits (Each bit drives one oscillator enable signal input of instance number 1, gated with RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.) */
10967+
#define RNG_NSCR_EN_OSC2_Pos (3UL)
10968+
#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */
10969+
#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk /*!< EN_OSC2[2:0] bits (Each bit drives one oscillator enable signal input of instance number 2, gated with RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.) */
10970+
#define RNG_NSCR_EN_OSC3_Pos (6UL)
10971+
#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */
10972+
#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk /*!< EN_OSC3[2:0] bits (Each bit drives one oscillator enable signal input of instance number 3, gated with RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.) */
10973+
#define RNG_NSCR_EN_OSC4_Pos (9UL)
10974+
#define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */
10975+
#define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk /*!< EN_OSC4[2:0] bits (Each bit drives one oscillator enable signal input of instance number 1, gated with RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.) */
10976+
#define RNG_NSCR_EN_OSC5_Pos (12UL)
10977+
#define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */
10978+
#define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk /*!< EN_OSC5[2:0] bits (Each bit drives one oscillator enable signal input of instance number 2, gated with RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.) */
10979+
#define RNG_NSCR_EN_OSC6_Pos (15UL)
10980+
#define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */
10981+
#define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk /*!< EN_OSC6[2:0] bits (Each bit drives one oscillator enable signal input of instance number 3, gated with RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.) */
10982+
1096310983
/******************** Bits definition for RNG_HTCR register *******************/
1096410984
#define RNG_HTCR_HTCFG_Pos (0UL)
1096510985
#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */
1096610986
#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk
10987+
1096710988
/******************** RNG Nist Compliance Values *******************/
1096810989
#define RNG_CR_NIST_VALUE (0x00F02D00U)
10990+
#define RNG_NSCR_NIST_VALUE (0x0003FFFFU)
1096910991
#define RNG_HTCR_NIST_VALUE (0xAAC7U)
1097010992

10971-
1097210993
/******************************************************************************/
1097310994
/* */
1097410995
/* Real-Time Clock (RTC) */

‎system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba55xx.h‎

Lines changed: 23 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -752,7 +752,7 @@ typedef struct
752752
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
753753
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
754754
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
755-
uint32_t RESERVED;
755+
__IO uint32_t NSCR; /*!< RNG noise source control register, Address offset: 0x0C */
756756
__IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */
757757
} RNG_TypeDef;
758758

@@ -10978,15 +10978,36 @@ typedef struct
1097810978
#define RNG_DR_RNDATA_Msk (0xFFFFFFFFUL << RNG_DR_RNDATA_Pos) /*!< 0xFFFFFFFF */
1097910979
#define RNG_DR_RNDATA RNG_DR_RNDATA_Msk
1098010980

10981+
/******************** Bit definition for RNG_NSCR register ********************/
10982+
#define RNG_NSCR_EN_OSC1_Pos (0UL)
10983+
#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */
10984+
#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk /*!< EN_OSC1[2:0] bits (Each bit drives one oscillator enable signal input of instance number 1, gated with RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.) */
10985+
#define RNG_NSCR_EN_OSC2_Pos (3UL)
10986+
#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */
10987+
#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk /*!< EN_OSC2[2:0] bits (Each bit drives one oscillator enable signal input of instance number 2, gated with RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.) */
10988+
#define RNG_NSCR_EN_OSC3_Pos (6UL)
10989+
#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */
10990+
#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk /*!< EN_OSC3[2:0] bits (Each bit drives one oscillator enable signal input of instance number 3, gated with RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.) */
10991+
#define RNG_NSCR_EN_OSC4_Pos (9UL)
10992+
#define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */
10993+
#define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk /*!< EN_OSC4[2:0] bits (Each bit drives one oscillator enable signal input of instance number 1, gated with RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.) */
10994+
#define RNG_NSCR_EN_OSC5_Pos (12UL)
10995+
#define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */
10996+
#define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk /*!< EN_OSC5[2:0] bits (Each bit drives one oscillator enable signal input of instance number 2, gated with RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.) */
10997+
#define RNG_NSCR_EN_OSC6_Pos (15UL)
10998+
#define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */
10999+
#define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk /*!< EN_OSC6[2:0] bits (Each bit drives one oscillator enable signal input of instance number 3, gated with RNGEN bit in RNG_CR (set bit to enable the oscillator). Bit is ignored otherwise.) */
11000+
1098111001
/******************** Bits definition for RNG_HTCR register *******************/
1098211002
#define RNG_HTCR_HTCFG_Pos (0UL)
1098311003
#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */
1098411004
#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk
11005+
1098511006
/******************** RNG Nist Compliance Values *******************/
1098611007
#define RNG_CR_NIST_VALUE (0x00F02D00U)
11008+
#define RNG_NSCR_NIST_VALUE (0x0003FFFFU)
1098711009
#define RNG_HTCR_NIST_VALUE (0xAAC7U)
1098811010

10989-
1099011011
/******************************************************************************/
1099111012
/* */
1099211013
/* Real-Time Clock (RTC) */

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