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feat(c5): configure 48MHz clock source #1403

feat(c5): configure 48MHz clock source

feat(c5): configure 48MHz clock source #1403

Triggered via pull request September 15, 2026 07:16
Status Success
Total duration 7m 33s
Artifacts –

PIO-build.yml

on: pull_request
PlatformIO test
7m 29s
PlatformIO test
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