From 5fbf2bfa171e8a2ec28ddd9064f36a14783fea8f Mon Sep 17 00:00:00 2001
From: Riccardo Borgani <44963821+rikyborg@users.noreply.github.com>
Date: Tue, 4 Aug 2026 15:47:39 +0200
Subject: [PATCH] set default=0 for DRACR, DRSR, IRACR, IRSR

---
 aarch32-cpu/src/register/dracr.rs | 2 +-
 aarch32-cpu/src/register/drsr.rs  | 2 +-
 aarch32-cpu/src/register/iracr.rs | 2 +-
 aarch32-cpu/src/register/irsr.rs  | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/aarch32-cpu/src/register/dracr.rs b/aarch32-cpu/src/register/dracr.rs
index f11e28a1..64147e9e 100644
--- a/aarch32-cpu/src/register/dracr.rs
+++ b/aarch32-cpu/src/register/dracr.rs
@@ -5,7 +5,7 @@ use arbitrary_int::u3;
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
 /// DRACR (*Data Region Access Control Register*)
-#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
+#[bitbybit::bitfield(u32, default = 0, debug, defmt_bitfields(feature = "defmt"))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Dracr {
     /// Execute Never
diff --git a/aarch32-cpu/src/register/drsr.rs b/aarch32-cpu/src/register/drsr.rs
index c9f2761e..1c94cf00 100644
--- a/aarch32-cpu/src/register/drsr.rs
+++ b/aarch32-cpu/src/register/drsr.rs
@@ -94,7 +94,7 @@ impl RegionSize {
 }
 
 /// DRSR (*Data Region Size and Enable Register*)
-#[bitbybit::bitfield(u32, debug, defmt_fields(feature = "defmt"))]
+#[bitbybit::bitfield(u32, default = 0, debug, defmt_fields(feature = "defmt"))]
 pub struct Drsr {
     /// Sub-region bitmask
     ///
diff --git a/aarch32-cpu/src/register/iracr.rs b/aarch32-cpu/src/register/iracr.rs
index 265bf622..43687e91 100644
--- a/aarch32-cpu/src/register/iracr.rs
+++ b/aarch32-cpu/src/register/iracr.rs
@@ -5,7 +5,7 @@ use arbitrary_int::u3;
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
 /// IRACR (*Instruction Region Access Control Register*)
-#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
+#[bitbybit::bitfield(u32, default = 0, debug, defmt_bitfields(feature = "defmt"))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Iracr {
     /// Execute Never
diff --git a/aarch32-cpu/src/register/irsr.rs b/aarch32-cpu/src/register/irsr.rs
index df9ba7e5..34508ded 100644
--- a/aarch32-cpu/src/register/irsr.rs
+++ b/aarch32-cpu/src/register/irsr.rs
@@ -5,7 +5,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 pub use super::drsr::RegionSize;
 
 /// IRSR (*Instruction Region Size and Enable Register*)
-#[bitbybit::bitfield(u32, debug, defmt_fields(feature = "defmt"))]
+#[bitbybit::bitfield(u32, default = 0, debug, defmt_fields(feature = "defmt"))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Irsr {
     /// Sub-region bitmask