Skip to content

Commit f7beaa7

Browse files
sgaud-quicsgaud-quic
authored
Merge pull request #247 from arakshit011/power-domain-for-ice
FROMLIST: Add explicit power-domain and clock voting for QCOM-ICE
2 parents c424fc5 + 7cb6270 commit f7beaa7

10 files changed

Lines changed: 73 additions & 9 deletions

File tree

‎Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml‎

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -28,12 +28,20 @@ properties:
2828
maxItems: 1
2929

3030
clocks:
31+
maxItems: 2
32+
33+
clock-names:
34+
maxItems: 2
35+
36+
power-domains:
3137
maxItems: 1
3238

3339
required:
3440
- compatible
3541
- reg
3642
- clocks
43+
- clock-names
44+
- power-domains
3745

3846
additionalProperties: false
3947

@@ -45,6 +53,10 @@ examples:
4553
compatible = "qcom,sm8550-inline-crypto-engine",
4654
"qcom,inline-crypto-engine";
4755
reg = <0x01d88000 0x8000>;
48-
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
56+
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
57+
<&gcc GCC_UFS_PHY_AHB_CLK>;
58+
clock-names = "ice_core_clk",
59+
"iface_clk";
60+
power-domains = <&gcc UFS_PHY_GDSC>;
4961
};
5062
...

‎arch/arm64/boot/dts/qcom/lemans.dtsi‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2774,7 +2774,11 @@
27742774
compatible = "qcom,sa8775p-inline-crypto-engine",
27752775
"qcom,inline-crypto-engine";
27762776
reg = <0x0 0x01d88000 0x0 0x18000>;
2777-
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2777+
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
2778+
<&gcc GCC_UFS_PHY_AHB_CLK>;
2779+
clock-names = "ice_core_clk",
2780+
"iface_clk";
2781+
power-domains = <&gcc UFS_PHY_GDSC>;
27782782
};
27792783

27802784
cryptobam: dma-controller@1dc4000 {

‎arch/arm64/boot/dts/qcom/monaco.dtsi‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2662,7 +2662,11 @@
26622662
compatible = "qcom,qcs8300-inline-crypto-engine",
26632663
"qcom,inline-crypto-engine";
26642664
reg = <0x0 0x01d88000 0x0 0x18000>;
2665-
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2665+
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
2666+
<&gcc GCC_UFS_PHY_AHB_CLK>;
2667+
clock-names = "ice_core_clk",
2668+
"iface_clk";
2669+
power-domains = <&gcc GCC_UFS_PHY_GDSC>;
26662670
};
26672671

26682672
crypto: crypto@1dfa000 {

‎arch/arm64/boot/dts/qcom/sc7180.dtsi‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1599,7 +1599,11 @@
15991599
compatible = "qcom,sc7180-inline-crypto-engine",
16001600
"qcom,inline-crypto-engine";
16011601
reg = <0 0x01d90000 0 0x8000>;
1602-
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
1602+
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
1603+
<&gcc GCC_UFS_PHY_AHB_CLK>;
1604+
clock-names = "ice_core_clk",
1605+
"iface_clk";
1606+
power-domains = <&gcc UFS_PHY_GDSC>;
16031607
};
16041608

16051609
ipa: ipa@1e40000 {

‎arch/arm64/boot/dts/qcom/sc7280.dtsi‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2579,7 +2579,11 @@
25792579
compatible = "qcom,sc7280-inline-crypto-engine",
25802580
"qcom,inline-crypto-engine";
25812581
reg = <0 0x01d88000 0 0x8000>;
2582-
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2582+
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
2583+
<&gcc GCC_UFS_PHY_AHB_CLK>;
2584+
clock-names = "ice_core_clk",
2585+
"iface_clk";
2586+
power-domains = <&gcc GCC_UFS_PHY_GDSC>;
25832587
};
25842588

25852589
cryptobam: dma-controller@1dc4000 {

‎arch/arm64/boot/dts/qcom/sm8450.dtsi‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5349,7 +5349,11 @@
53495349
compatible = "qcom,sm8450-inline-crypto-engine",
53505350
"qcom,inline-crypto-engine";
53515351
reg = <0 0x01d88000 0 0x8000>;
5352-
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
5352+
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
5353+
<&gcc GCC_UFS_PHY_AHB_CLK>;
5354+
clock-names = "ice_core_clk",
5355+
"iface_clk";
5356+
power-domains = <&gcc UFS_PHY_GDSC>;
53535357
};
53545358

53555359
cryptobam: dma-controller@1dc4000 {

‎arch/arm64/boot/dts/qcom/sm8550.dtsi‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2414,7 +2414,11 @@
24142414
"qcom,inline-crypto-engine";
24152415
reg = <0 0x01d88000 0 0x18000>;
24162416

2417-
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2417+
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
2418+
<&gcc GCC_UFS_PHY_AHB_CLK>;
2419+
clock-names = "ice_core_clk",
2420+
"iface_clk";
2421+
power-domains = <&gcc UFS_PHY_GDSC>;
24182422
};
24192423

24202424
tcsr_mutex: hwlock@1f40000 {

‎arch/arm64/boot/dts/qcom/sm8650.dtsi‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4046,7 +4046,11 @@
40464046
"qcom,inline-crypto-engine";
40474047
reg = <0 0x01d88000 0 0x18000>;
40484048

4049-
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
4049+
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
4050+
<&gcc GCC_UFS_PHY_AHB_CLK>;
4051+
clock-names = "ice_core_clk",
4052+
"iface_clk";
4053+
power-domains = <&gcc UFS_PHY_GDSC>;
40504054
};
40514055

40524056
cryptobam: dma-controller@1dc4000 {

‎arch/arm64/boot/dts/qcom/sm8750.dtsi‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2058,7 +2058,11 @@
20582058
"qcom,inline-crypto-engine";
20592059
reg = <0x0 0x01d88000 0x0 0x18000>;
20602060

2061-
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2061+
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
2062+
<&gcc GCC_UFS_PHY_AHB_CLK>;
2063+
clock-names = "ice_core_clk",
2064+
"iface_clk";
2065+
power-domains = <&gcc GCC_UFS_PHY_GDSC>;
20622066
};
20632067

20642068
cryptobam: dma-controller@1dc4000 {

‎drivers/soc/qcom/ice.c‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,8 @@
1616
#include <linux/of.h>
1717
#include <linux/of_platform.h>
1818
#include <linux/platform_device.h>
19+
#include <linux/pm.h>
20+
#include <linux/pm_runtime.h>
1921

2022
#include <linux/firmware/qcom/qcom_scm.h>
2123

@@ -108,6 +110,7 @@ struct qcom_ice {
108110
void __iomem *base;
109111

110112
struct clk *core_clk;
113+
struct clk *iface_clk;
111114
bool use_hwkm;
112115
bool hwkm_init_complete;
113116
u8 hwkm_version;
@@ -310,20 +313,30 @@ int qcom_ice_resume(struct qcom_ice *ice)
310313
struct device *dev = ice->dev;
311314
int err;
312315

316+
pm_runtime_get_sync(dev);
313317
err = clk_prepare_enable(ice->core_clk);
314318
if (err) {
315319
dev_err(dev, "failed to enable core clock (%d)\n",
316320
err);
317321
return err;
318322
}
323+
324+
err = clk_prepare_enable(ice->iface_clk);
325+
if (err) {
326+
dev_err(dev, "failed to enable iface clock (%d)\n",
327+
err);
328+
return err;
329+
}
319330
qcom_ice_hwkm_init(ice);
320331
return qcom_ice_wait_bist_status(ice);
321332
}
322333
EXPORT_SYMBOL_GPL(qcom_ice_resume);
323334

324335
int qcom_ice_suspend(struct qcom_ice *ice)
325336
{
337+
clk_disable_unprepare(ice->iface_clk);
326338
clk_disable_unprepare(ice->core_clk);
339+
pm_runtime_put_sync(ice->dev);
327340
ice->hwkm_init_complete = false;
328341

329342
return 0;
@@ -584,6 +597,10 @@ static struct qcom_ice *qcom_ice_create(struct device *dev,
584597
if (IS_ERR(engine->core_clk))
585598
return ERR_CAST(engine->core_clk);
586599

600+
engine->iface_clk = devm_clk_get_enabled(dev, "iface_clk");
601+
if (IS_ERR(engine->iface_clk))
602+
return ERR_CAST(engine->iface_clk);
603+
587604
if (!qcom_ice_check_supported(engine))
588605
return ERR_PTR(-EOPNOTSUPP);
589606

@@ -725,6 +742,9 @@ static int qcom_ice_probe(struct platform_device *pdev)
725742
return PTR_ERR(base);
726743
}
727744

745+
devm_pm_runtime_enable(&pdev->dev);
746+
pm_runtime_get_sync(&pdev->dev);
747+
728748
engine = qcom_ice_create(&pdev->dev, base);
729749
if (IS_ERR(engine))
730750
return PTR_ERR(engine);

0 commit comments

Comments
 (0)