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arm64: dts: qcom: add staging DT overlays for QPS615 enablement (#335)
arm64: dts: qcom: add staging DT overlays for QPS615 enablement
2 parents e624dc5 + d4bb439 commit d631c6b

4 files changed

Lines changed: 237 additions & 0 deletions

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‎arch/arm64/boot/dts/qcom/Makefile‎

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@@ -423,6 +423,8 @@ lemans-camx-el2-dtbs := lemans-evk-el2.dtb lemans-evk-camx.dtbo lemans-camx-el2.
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dtb-$(CONFIG_ARCH_QCOM) += lemans-camx-el2.dtb
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dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-staging.dtbo
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monaco-evk-camx-dtbs := monaco-evk.dtb monaco-evk-camx.dtbo
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dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-camx.dtb
@@ -431,6 +433,8 @@ monaco-camx-el2-dtbs := monaco-evk-el2.dtb monaco-evk-camx.dtbo monaco-camx-el2.
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dtb-$(CONFIG_ARCH_QCOM) += monaco-camx-el2.dtb
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dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-staging.dtbo
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qcs615-ride-camx-dtbs := qcs615-ride.dtb qcs615-ride-camx.dtbo
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dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride-camx.dtb
@@ -440,6 +444,8 @@ qcs6490-rb3gen2-vision-mezzanine-camx-dtbs := qcs6490-rb3gen2-vision-mezzanine.d
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dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-vision-mezzanine-camx.dtb
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dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-staging.dtbo
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qcs8300-ride-camx-dtbs:= qcs8300-ride.dtb qcs8300-ride-camx.dtbo
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dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride-camx.dtb

‎arch/arm64/boot/dts/qcom/lemans-evk-staging.dtso‎

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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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&i2c18 {
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eeprom@52 {
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nvmem-layout {
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mac_addr2: mac-addr@6 {
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reg = <0x6 0x6>;
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};
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mac_addr3: mac-addr@c {
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reg = <0xc 0x6>;
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};
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};
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};
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};
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&pcieport0 {
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pcie@0,0 {
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pcie@3,0 {
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pci@0,0 {
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interrupts-extended = <&tlmm 56 IRQ_TYPE_EDGE_FALLING>;
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interrupt-names = "wol_irq";
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nvmem-cells = <&mac_addr2>;
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nvmem-cell-names = "mac-address";
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pinctrl-names = "default";
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pinctrl-0 = <&aqr_intn_wol_sig>;
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phy-reset-gpios = <&tlmm 76 GPIO_ACTIVE_HIGH>;
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reset-deassert-us = <221000>;
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};
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pci@0,1 {
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interrupts-extended = <&tlmm 57 IRQ_TYPE_EDGE_FALLING>;
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interrupt-names = "wol_irq";
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nvmem-cells = <&mac_addr3>;
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nvmem-cell-names = "mac-address";
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pinctrl-names = "default";
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pinctrl-0 = <&napa_intn_wol_sig>;
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phy-reset-gpios = <&tlmm 77 GPIO_ACTIVE_HIGH>;
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reset-deassert-us = <20000>;
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};
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};
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};
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};
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&tlmm {
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qps615_intn_wol {
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aqr_intn_wol_sig: aqr-intn-wol-sig {
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pins = "gpio56";
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function = "gpio";
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input-enable;
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bias-disable;
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};
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napa_intn_wol_sig: napa-intn-wol-sig {
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pins = "gpio57";
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function = "gpio";
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input-enable;
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bias-disable;
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};
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};
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};

‎arch/arm64/boot/dts/qcom/monaco-evk-staging.dtso‎

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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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&eeprom1 {
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nvmem-layout {
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mac_addr1: mac-addr@0 {
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reg = <0x0 0x6>;
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};
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mac_addr2: mac-addr@6 {
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reg = <0x6 0x6>;
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};
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};
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};
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&pcieport0 {
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pcie@0,0 {
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pcie@3,0 {
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pci@0,0 {
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interrupts-extended = <&tlmm 40 IRQ_TYPE_EDGE_FALLING>;
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interrupt-names = "wol_irq";
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nvmem-cells = <&mac_addr1>;
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nvmem-cell-names = "mac-address";
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pinctrl-names = "default";
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pinctrl-0 = <&aqr_intn_wol_sig>;
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phy-reset-gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>;
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reset-deassert-us = <221000>;
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};
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pci@0,1 {
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interrupts-extended = <&tlmm 39 IRQ_TYPE_EDGE_FALLING>;
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interrupt-names = "wol_irq";
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nvmem-cells = <&mac_addr2>;
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nvmem-cell-names = "mac-address";
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pinctrl-names = "default";
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pinctrl-0 = <&napa_intn_wol_sig>;
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phy-reset-gpios = <&expander5 0 GPIO_ACTIVE_HIGH>;
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reset-deassert-us = <20000>;
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};
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};
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};
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};
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&tlmm {
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qps615_intn_wol {
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aqr_intn_wol_sig: aqr-intn-wol-sig {
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pins = "gpio40";
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function = "gpio";
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input-enable;
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bias-disable;
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};
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napa_intn_wol_sig: napa-intn-wol-sig {
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pins = "gpio39";
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function = "gpio";
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input-enable;
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bias-disable;
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};
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};
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};

‎arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-staging.dtso‎

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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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qep_vreg: qep_vreg {
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compatible = "regulator-fixed";
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regulator-name = "qep_vreg";
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gpio = <&pm7325_gpios 8 0>;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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enable-active-high;
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};
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aqr_vreg: aqr_vreg {
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compatible = "regulator-fixed";
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regulator-name = "aqr_vreg";
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gpio = <&pm7250b_gpios 4 0>;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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enable-active-high;
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};
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};
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&pcie1_port0 {
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pcie@0,0 {
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pcie@3,0 {
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/*
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* PF0: also acts as the QPS615 GPIO controller.
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* gpio-controller / #gpio-cells expose the TC956X
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* internal GPIO lines (hardware numbers 0-13) so that
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* phy-reset-gpios can reference them.
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*/
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qps615: pci@0,0 {
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interrupts-extended = <&tlmm 141 IRQ_TYPE_EDGE_FALLING>;
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interrupt-names = "wol_irq";
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phy-supply = <&aqr_vreg>;
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pinctrl-names = "default";
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pinctrl-0 = <&aqr_intn_wol_sig>;
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phy-reset-gpios = <&qps615 0 GPIO_ACTIVE_LOW>;
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reset-deassert-us = <221000>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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pci@0,1 {
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interrupts-extended = <&tlmm 101 IRQ_TYPE_EDGE_FALLING>;
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interrupt-names = "wol_irq";
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phy-supply = <&qep_vreg>;
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pinctrl-names = "default";
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pinctrl-0 = <&napa_intn_wol_sig>;
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phy-reset-gpios = <&qps615 1 GPIO_ACTIVE_LOW>;
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reset-deassert-us = <20000>;
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};
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};
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};
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};
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&tlmm {
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qps615_intn_wol {
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aqr_intn_wol_sig: aqr_intn_wol_sig {
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mux {
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pins = "gpio141";
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function = "gpio";
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};
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config {
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pins = "gpio141";
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input-enable;
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bias-disable;
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};
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};
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napa_intn_wol_sig: napa_intn_wol_sig {
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mux {
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pins = "gpio101";
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function = "gpio";
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};
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config {
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pins = "gpio101";
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input-enable;
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bias-disable;
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};
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};
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};
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};

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