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Merge pull request #267 from ayaan-anwar/talos_eth
Enable ethernet on Talos Ride SX
2 parents 87612eb + 361fefe commit d0c752c

3 files changed

Lines changed: 145 additions & 5 deletions

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arch/arm64/boot/dts/qcom/qcs615-ride.dts

Lines changed: 102 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -372,6 +372,59 @@
372372
};
373373
};
374374

375+
&ethernet {
376+
pinctrl-0 = <&ethernet_defaults>;
377+
pinctrl-names = "default";
378+
379+
phy-handle = <&rgmii_phy>;
380+
phy-mode = "rgmii-id";
381+
382+
snps,mtl-rx-config = <&mtl_rx_setup>;
383+
snps,mtl-tx-config = <&mtl_tx_setup>;
384+
385+
status = "okay";
386+
387+
mdio: mdio {
388+
compatible = "snps,dwmac-mdio";
389+
#address-cells = <1>;
390+
#size-cells = <0>;
391+
392+
rgmii_phy: phy@7 {
393+
compatible = "ethernet-phy-ieee802.3-c22";
394+
reg = <0x7>;
395+
396+
interrupts-extended = <&tlmm 121 IRQ_TYPE_EDGE_FALLING>;
397+
device_type = "ethernet-phy";
398+
reset-gpios = <&tlmm 104 GPIO_ACTIVE_LOW>;
399+
reset-assert-us = <11000>;
400+
reset-deassert-us = <70000>;
401+
};
402+
};
403+
404+
mtl_rx_setup: rx-queues-config {
405+
snps,rx-queues-to-use = <1>;
406+
snps,rx-sched-sp;
407+
408+
queue0 {
409+
snps,dcb-algorithm;
410+
snps,map-to-dma-channel = <0x0>;
411+
snps,route-up;
412+
snps,priority = <0x1>;
413+
};
414+
};
415+
416+
mtl_tx_setup: tx-queues-config {
417+
snps,tx-queues-to-use = <1>;
418+
snps,tx-sched-wrr;
419+
420+
queue0 {
421+
snps,weight = <0x10>;
422+
snps,dcb-algorithm;
423+
snps,priority = <0x0>;
424+
};
425+
};
426+
};
427+
375428
&gpu {
376429
status = "okay";
377430
};
@@ -552,6 +605,55 @@
552605
};
553606

554607
&tlmm {
608+
ethernet_defaults: ethernet-defaults-state {
609+
mdc-pins {
610+
pins = "gpio113";
611+
function = "rgmii";
612+
bias-pull-up;
613+
};
614+
615+
mdio-pins {
616+
pins = "gpio114";
617+
function = "rgmii";
618+
bias-pull-up;
619+
};
620+
621+
rgmii-rx-pins {
622+
pins = "gpio81", "gpio82", "gpio83", "gpio102", "gpio103", "gpio112";
623+
function = "rgmii";
624+
bias-disable;
625+
drive-strength = <2>;
626+
};
627+
628+
rgmii-tx-pins {
629+
pins = "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97";
630+
function = "rgmii";
631+
bias-pull-up;
632+
drive-strength = <16>;
633+
};
634+
635+
phy-intr-pins {
636+
pins = "gpio121";
637+
function = "gpio";
638+
bias-disable;
639+
drive-strength = <8>;
640+
};
641+
642+
pps-pins {
643+
pins = "gpio91";
644+
function = "rgmii";
645+
bias-disable;
646+
drive-strength = <8>;
647+
};
648+
649+
phy-reset-pins {
650+
pins = "gpio104";
651+
function = "gpio";
652+
bias-pull-up;
653+
drive-strength = <16>;
654+
};
655+
};
656+
555657
bt_en_state: bt-en-state {
556658
pins = "gpio85";
557659
function = "gpio";

arch/arm64/boot/dts/qcom/talos.dtsi

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -678,6 +678,40 @@
678678
#address-cells = <2>;
679679
#size-cells = <2>;
680680

681+
ethernet: ethernet@20000 {
682+
compatible = "qcom,qcs615-ethqos", "qcom,qcs404-ethqos";
683+
reg = <0x0 0x00020000 0x0 0x10000>,
684+
<0x0 0x00036000 0x0 0x100>;
685+
reg-names = "stmmaceth",
686+
"rgmii";
687+
688+
clocks = <&gcc GCC_EMAC_AXI_CLK>,
689+
<&gcc GCC_EMAC_SLV_AHB_CLK>,
690+
<&gcc GCC_EMAC_PTP_CLK>,
691+
<&gcc GCC_EMAC_RGMII_CLK>;
692+
clock-names = "stmmaceth",
693+
"pclk",
694+
"ptp_ref",
695+
"rgmii";
696+
697+
interrupts = <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH 0>,
698+
<GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH 0>;
699+
interrupt-names = "macirq",
700+
"eth_lpi";
701+
702+
power-domains = <&gcc EMAC_GDSC>;
703+
resets = <&gcc GCC_EMAC_BCR>;
704+
705+
iommus = <&apps_smmu 0x1c0 0x0>;
706+
707+
snps,tso;
708+
snps,pbl = <32>;
709+
rx-fifo-depth = <16384>;
710+
tx-fifo-depth = <20480>;
711+
712+
status = "disabled";
713+
};
714+
681715
gcc: clock-controller@100000 {
682716
compatible = "qcom,qcs615-gcc";
683717
reg = <0 0x00100000 0 0x1f0000>;

drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c

Lines changed: 9 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -387,14 +387,11 @@ static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
387387
static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed)
388388
{
389389
struct device *dev = &ethqos->pdev->dev;
390-
int phase_shift;
390+
int phase_shift = 0;
391391
int loopback;
392392

393393
/* Determine if the PHY adds a 2 ns TX delay or the MAC handles it */
394-
if (ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_ID ||
395-
ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_TXID)
396-
phase_shift = 0;
397-
else
394+
if (ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
398395
phase_shift = RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN;
399396

400397
/* Disable loopback mode */
@@ -789,7 +786,14 @@ static int qcom_ethqos_probe(struct platform_device *pdev)
789786
if (!ethqos)
790787
return -ENOMEM;
791788

789+
/* Qualcomm configures the MAC to introduce delay; instruct the
790+
* PHY not to add additional delay.
791+
*/
792+
if (plat_dat->phy_interface == PHY_INTERFACE_MODE_RGMII_ID)
793+
plat_dat->phy_interface = PHY_INTERFACE_MODE_RGMII;
794+
792795
ethqos->phy_mode = plat_dat->phy_interface;
796+
793797
switch (ethqos->phy_mode) {
794798
case PHY_INTERFACE_MODE_RGMII:
795799
case PHY_INTERFACE_MODE_RGMII_ID:

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