Skip to content

Commit bb04523

Browse files
sgaud-quicsgaud-quic
authored
Merge pull request #137 from jiezh-qualcomm/a612_support_qli2.0
A612 support on qli2.0
2 parents f6285e2 + 05854b0 commit bb04523

10 files changed

Lines changed: 566 additions & 227 deletions

File tree

‎Documentation/devicetree/bindings/display/msm/gpu.yaml‎

Lines changed: 64 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -45,11 +45,11 @@ properties:
4545
- const: amd,imageon
4646
4747
clocks:
48-
minItems: 2
48+
minItems: 1
4949
maxItems: 7
5050

5151
clock-names:
52-
minItems: 2
52+
minItems: 1
5353
maxItems: 7
5454

5555
reg:
@@ -388,26 +388,68 @@ allOf:
388388
required:
389389
- clocks
390390
- clock-names
391-
else:
392-
if:
393-
properties:
394-
compatible:
395-
contains:
396-
oneOf:
397-
- pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]+$'
398-
- pattern: '^qcom,adreno-[0-9a-f]{8}$'
399-
400-
then: # Starting with A6xx, the clocks are usually defined in the GMU node
401-
properties:
402-
clocks: false
403-
clock-names: false
404-
405-
reg-names:
406-
minItems: 1
407-
items:
408-
- const: kgsl_3d0_reg_memory
409-
- const: cx_mem
410-
- const: cx_dbgc
391+
392+
- if:
393+
properties:
394+
compatible:
395+
contains:
396+
const: qcom,adreno-612.0
397+
then:
398+
properties:
399+
clocks:
400+
items:
401+
- description: GPU Core clock
402+
403+
clock-names:
404+
items:
405+
- const: core
406+
407+
reg-names:
408+
minItems: 1
409+
items:
410+
- const: kgsl_3d0_reg_memory
411+
- const: cx_mem
412+
- const: cx_dbgc
413+
414+
required:
415+
- clocks
416+
- clock-names
417+
418+
- if:
419+
properties:
420+
compatible:
421+
contains:
422+
enum:
423+
- qcom,adreno-615.0
424+
- qcom,adreno-618.0
425+
- qcom,adreno-619.0
426+
- qcom,adreno-621.0
427+
- qcom,adreno-623.0
428+
- qcom,adreno-630.2
429+
- qcom,adreno-635.0
430+
- qcom,adreno-640.1
431+
- qcom,adreno-650.2
432+
- qcom,adreno-660.1
433+
- qcom,adreno-663.0
434+
- qcom,adreno-680.1
435+
- qcom,adreno-690.0
436+
- qcom,adreno-730.1
437+
- qcom,adreno-43030c00
438+
- qcom,adreno-43050a01
439+
- qcom,adreno-43050c01
440+
- qcom,adreno-43051401
441+
442+
then: # Starting with A6xx, the clocks are usually defined in the GMU node
443+
properties:
444+
clocks: false
445+
clock-names: false
446+
447+
reg-names:
448+
minItems: 1
449+
items:
450+
- const: kgsl_3d0_reg_memory
451+
- const: cx_mem
452+
- const: cx_dbgc
411453

412454
examples:
413455
- |

‎Documentation/devicetree/bindings/display/msm/qcom,adreno-rgmu.yaml‎

Lines changed: 126 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,126 @@
1+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2+
# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
3+
%YAML 1.2
4+
---
5+
6+
$id: http://devicetree.org/schemas/display/msm/qcom,adreno-rgmu.yaml#
7+
$schema: http://devicetree.org/meta-schemas/core.yaml#
8+
9+
title: RGMU attached to certain Adreno GPUs
10+
11+
maintainers:
12+
- Rob Clark <robin.clark@oss.qualcomm.com>
13+
14+
description:
15+
RGMU (Reduced Graphics Management Unit) IP is present in some GPUs that
16+
belong to Adreno A6xx family. It is a small state machine that helps to
17+
toggle the GX GDSC (connected to CX rail) to implement IFPC feature and save
18+
power.
19+
20+
properties:
21+
compatible:
22+
items:
23+
- const: qcom,adreno-rgmu-612.0
24+
- const: qcom,adreno-rgmu
25+
26+
reg:
27+
items:
28+
- description: Core RGMU registers
29+
30+
clocks:
31+
items:
32+
- description: GMU clock
33+
- description: GPU CX clock
34+
- description: GPU AXI clock
35+
- description: GPU MEMNOC clock
36+
- description: GPU SMMU vote clock
37+
38+
clock-names:
39+
items:
40+
- const: gmu
41+
- const: cxo
42+
- const: axi
43+
- const: memnoc
44+
- const: smmu_vote
45+
46+
power-domains:
47+
items:
48+
- description: CX GDSC power domain
49+
- description: GX GDSC power domain
50+
51+
power-domain-names:
52+
items:
53+
- const: cx
54+
- const: gx
55+
56+
interrupts:
57+
items:
58+
- description: GMU OOB interrupt
59+
- description: GMU interrupt
60+
61+
interrupt-names:
62+
items:
63+
- const: oob
64+
- const: gmu
65+
66+
operating-points-v2: true
67+
opp-table:
68+
type: object
69+
70+
required:
71+
- compatible
72+
- reg
73+
- clocks
74+
- clock-names
75+
- power-domains
76+
- power-domain-names
77+
- interrupts
78+
- interrupt-names
79+
- operating-points-v2
80+
81+
additionalProperties: false
82+
83+
examples:
84+
- |
85+
#include <dt-bindings/clock/qcom,qcs615-gpucc.h>
86+
#include <dt-bindings/clock/qcom,qcs615-gcc.h>
87+
#include <dt-bindings/interrupt-controller/arm-gic.h>
88+
#include <dt-bindings/power/qcom,rpmhpd.h>
89+
90+
gmu@506a000 {
91+
compatible = "qcom,adreno-rgmu-612.0", "qcom,adreno-rgmu";
92+
93+
reg = <0x05000000 0x90000>;
94+
95+
clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
96+
<&gpucc GPU_CC_CXO_CLK>,
97+
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
98+
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
99+
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
100+
clock-names = "gmu",
101+
"cxo",
102+
"axi",
103+
"memnoc",
104+
"smmu_vote";
105+
106+
power-domains = <&gpucc CX_GDSC>,
107+
<&gpucc GX_GDSC>;
108+
power-domain-names = "cx",
109+
"gx";
110+
111+
interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
112+
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
113+
interrupt-names = "oob",
114+
"gmu";
115+
116+
operating-points-v2 = <&gmu_opp_table>;
117+
118+
gmu_opp_table: opp-table {
119+
compatible = "operating-points-v2";
120+
121+
opp-200000000 {
122+
opp-hz = /bits/ 64 <200000000>;
123+
required-opps = <&rpmhpd_opp_low_svs>;
124+
};
125+
};
126+
};

‎MAINTAINERS‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7884,6 +7884,7 @@ S: Maintained
78847884
B: https://gitlab.freedesktop.org/drm/msm/-/issues
78857885
T: git https://gitlab.freedesktop.org/drm/msm.git
78867886
F: Documentation/devicetree/bindings/display/msm/gpu.yaml
7887+
F: Documentation/devicetree/bindings/display/msm/qcom,adreno-rgmu.yaml
78877888
F: Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml
78887889
F: drivers/gpu/drm/msm/adreno/
78897890
F: drivers/gpu/drm/msm/msm_gpu.*

‎arch/arm64/boot/dts/qcom/qcs615-ride.dts‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -372,6 +372,14 @@
372372
};
373373
};
374374

375+
&gpu {
376+
status = "okay";
377+
};
378+
379+
&gpu_zap_shader {
380+
firmware-name = "qcom/qcs615/a612_zap.mbn";
381+
};
382+
375383
&i2c2 {
376384
clock-frequency = <400000>;
377385
status = "okay";

0 commit comments

Comments
 (0)