Skip to content

Commit abf62a5

Browse files
rlaggyshRaviteja Laggyshetty
rlaggysh
authored and
Raviteja Laggyshetty
committed
BACKPORT: FROM GIT: arm64: dts: qcom: qcs615: Add OSM l3 interconnect provider node and CPU OPP tables to scale DDR/L3
Add Operation State Manager (OSM) L3 interconnect provide node and OPP tables required to scale DDR and L3 per freq-domain on QCS615 SoC. As QCS615 and SM8150 SoCs have same OSM hardware, added SM8150 compatible as fallback for QCS615 OSM device node. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250819-talos-l3-icc-v3-2-04529e85dac7@oss.qualcomm.com
1 parent 8dd59c5 commit abf62a5

1 file changed

Lines changed: 148 additions & 0 deletions

File tree

‎arch/arm64/boot/dts/qcom/talos.dtsi‎

Lines changed: 148 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@
1212
#include <dt-bindings/clock/qcom,rpmh.h>
1313
#include <dt-bindings/dma/qcom-gpi.h>
1414
#include <dt-bindings/interconnect/qcom,icc.h>
15+
#include <dt-bindings/interconnect/qcom,osm-l3.h>
1516
#include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
1617
#include <dt-bindings/interrupt-controller/arm-gic.h>
1718
#include <dt-bindings/phy/phy-qcom-qmp.h>
@@ -41,6 +42,10 @@
4142
clocks = <&cpufreq_hw 0>;
4243
qcom,freq-domain = <&cpufreq_hw 0>;
4344
#cooling-cells = <2>;
45+
operating-points-v2 = <&cpu0_opp_table>;
46+
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
47+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
48+
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
4449

4550
l2_0: l2-cache {
4651
compatible = "cache";
@@ -62,6 +67,10 @@
6267
next-level-cache = <&l2_100>;
6368
clocks = <&cpufreq_hw 0>;
6469
qcom,freq-domain = <&cpufreq_hw 0>;
70+
operating-points-v2 = <&cpu0_opp_table>;
71+
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
72+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
73+
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
6574

6675
l2_100: l2-cache {
6776
compatible = "cache";
@@ -83,6 +92,10 @@
8392
next-level-cache = <&l2_200>;
8493
clocks = <&cpufreq_hw 0>;
8594
qcom,freq-domain = <&cpufreq_hw 0>;
95+
operating-points-v2 = <&cpu0_opp_table>;
96+
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
97+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
98+
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
8699

87100
l2_200: l2-cache {
88101
compatible = "cache";
@@ -104,6 +117,10 @@
104117
next-level-cache = <&l2_300>;
105118
clocks = <&cpufreq_hw 0>;
106119
qcom,freq-domain = <&cpufreq_hw 0>;
120+
operating-points-v2 = <&cpu0_opp_table>;
121+
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
122+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
123+
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
107124

108125
l2_300: l2-cache {
109126
compatible = "cache";
@@ -125,6 +142,10 @@
125142
next-level-cache = <&l2_400>;
126143
clocks = <&cpufreq_hw 0>;
127144
qcom,freq-domain = <&cpufreq_hw 0>;
145+
operating-points-v2 = <&cpu0_opp_table>;
146+
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
147+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
148+
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
128149

129150
l2_400: l2-cache {
130151
compatible = "cache";
@@ -146,6 +167,10 @@
146167
next-level-cache = <&l2_500>;
147168
clocks = <&cpufreq_hw 0>;
148169
qcom,freq-domain = <&cpufreq_hw 0>;
170+
operating-points-v2 = <&cpu0_opp_table>;
171+
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
172+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
173+
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
149174

150175
l2_500: l2-cache {
151176
compatible = "cache";
@@ -168,6 +193,10 @@
168193
clocks = <&cpufreq_hw 1>;
169194
qcom,freq-domain = <&cpufreq_hw 1>;
170195
#cooling-cells = <2>;
196+
operating-points-v2 = <&cpu6_opp_table>;
197+
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
198+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
199+
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
171200

172201
l2_600: l2-cache {
173202
compatible = "cache";
@@ -189,6 +218,10 @@
189218
next-level-cache = <&l2_700>;
190219
clocks = <&cpufreq_hw 1>;
191220
qcom,freq-domain = <&cpufreq_hw 1>;
221+
operating-points-v2 = <&cpu6_opp_table>;
222+
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
223+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
224+
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
192225

193226
l2_700: l2-cache {
194227
compatible = "cache";
@@ -241,6 +274,111 @@
241274
};
242275
};
243276

277+
cpu0_opp_table: opp-table-cpu0 {
278+
compatible = "operating-points-v2";
279+
opp-shared;
280+
281+
opp-300000000 {
282+
opp-hz = /bits/ 64 <300000000>;
283+
opp-peak-kBps = <(300000 * 4) (300000 * 16)>;
284+
};
285+
286+
opp-576000000 {
287+
opp-hz = /bits/ 64 <576000000>;
288+
opp-peak-kBps = <(300000 * 4) (576000 * 16)>;
289+
};
290+
291+
opp-748800000 {
292+
opp-hz = /bits/ 64 <748800000>;
293+
opp-peak-kBps = <(300000 * 4) (576000 * 16)>;
294+
};
295+
296+
opp-998400000 {
297+
opp-hz = /bits/ 64 <998400000>;
298+
opp-peak-kBps = <(451000 * 4) (806400 * 16)>;
299+
};
300+
301+
opp-1209600000 {
302+
opp-hz = /bits/ 64 <1209600000>;
303+
opp-peak-kBps = <(547000 * 4) (1017600 * 16)>;
304+
};
305+
306+
opp-1363200000 {
307+
opp-hz = /bits/ 64 <1363200000>;
308+
opp-peak-kBps = <(768000 * 4) (1209600 * 16)>;
309+
};
310+
311+
opp-1516800000 {
312+
opp-hz = /bits/ 64 <1516800000>;
313+
opp-peak-kBps = <(768000 * 4) (1209600 * 16)>;
314+
};
315+
316+
opp-1593600000 {
317+
opp-hz = /bits/ 64 <1593600000>;
318+
opp-peak-kBps = <(1017000 * 4) (1363200 * 16)>;
319+
};
320+
};
321+
322+
cpu6_opp_table: opp-table-cpu6 {
323+
compatible = "operating-points-v2";
324+
opp-shared;
325+
326+
opp-300000000 {
327+
opp-hz = /bits/ 64 <300000000>;
328+
opp-peak-kBps = <(451000 * 4) (300000 * 16)>;
329+
};
330+
331+
opp-652800000 {
332+
opp-hz = /bits/ 64 <652800000>;
333+
opp-peak-kBps = <(451000 * 4) (576000 * 16)>;
334+
};
335+
336+
opp-768000000 {
337+
opp-hz = /bits/ 64 <768000000>;
338+
opp-peak-kBps = <(451000 * 4) (576000 * 16)>;
339+
};
340+
341+
opp-979200000 {
342+
opp-hz = /bits/ 64 <979200000>;
343+
opp-peak-kBps = <(547000 * 4) (806400 * 16)>;
344+
};
345+
346+
opp-1017600000 {
347+
opp-hz = /bits/ 64 <1017600000>;
348+
opp-peak-kBps = <(547000 * 4) (806400 * 16)>;
349+
};
350+
351+
opp-1094400000 {
352+
opp-hz = /bits/ 64 <109440000>;
353+
opp-peak-kBps = <(1017600 * 4) (940800 * 16)>;
354+
};
355+
356+
opp-1209600000 {
357+
opp-hz = /bits/ 64 <1209600000>;
358+
opp-peak-kBps = <(1017600 * 4) (1017600 * 16)>;
359+
};
360+
361+
opp-1363200000 {
362+
opp-hz = /bits/ 64 <1363200000>;
363+
opp-peak-kBps = <(1555000 * 4) (1209600 * 16)>;
364+
};
365+
366+
opp-1516800000 {
367+
opp-hz = /bits/ 64 <1516800000>;
368+
opp-peak-kBps = <(1555000 * 4) (1209600 * 16)>;
369+
};
370+
371+
opp-1708800000 {
372+
opp-hz = /bits/ 64 <1708800000>;
373+
opp-peak-kBps = <(1555000 * 4) (1363200 * 16)>;
374+
};
375+
376+
opp-1900800000 {
377+
opp-hz = /bits/ 64 <1900800000>;
378+
opp-peak-kBps = <(1555000 * 4) (1363200 * 16)>;
379+
};
380+
};
381+
244382
dummy_eud: dummy-sink {
245383
compatible = "arm,coresight-dummy-sink";
246384

@@ -4240,6 +4378,16 @@
42404378
};
42414379
};
42424380

4381+
osm_l3: interconnect@18321000 {
4382+
compatible = "qcom,qcs615-osm-l3", "qcom,sm8150-osm-l3", "qcom,osm-l3";
4383+
reg = <0x0 0x18321000 0x0 0x1400>;
4384+
4385+
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4386+
clock-names = "xo", "alternate";
4387+
4388+
#interconnect-cells = <1>;
4389+
};
4390+
42434391
usb_1_hsphy: phy@88e2000 {
42444392
compatible = "qcom,qcs615-qusb2-phy";
42454393
reg = <0x0 0x88e2000 0x0 0x180>;

0 commit comments

Comments
 (0)