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| 1 | +// SPDX-License-Identifier: BSD-3-Clause |
| 2 | +/* |
| 3 | + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. |
| 4 | + */ |
| 5 | + |
| 6 | +/dts-v1/; |
| 7 | +/plugin/; |
| 8 | + |
| 9 | +#include <dt-bindings/gpio/gpio.h> |
| 10 | + |
| 11 | +&{/} { |
| 12 | + model = "Qualcomm Technologies, Inc. Lemans-evk Mezzanine"; |
| 13 | + |
| 14 | + vreg_0p9: regulator-vreg-0p9 { |
| 15 | + compatible = "regulator-fixed"; |
| 16 | + regulator-name = "VREG_0P9"; |
| 17 | + |
| 18 | + regulator-min-microvolt = <900000>; |
| 19 | + regulator-max-microvolt = <900000>; |
| 20 | + regulator-always-on; |
| 21 | + regulator-boot-on; |
| 22 | + |
| 23 | + vin-supply = <&vreg_3p3>; |
| 24 | + }; |
| 25 | + |
| 26 | + vreg_1p8: regulator-vreg-1p8 { |
| 27 | + compatible = "regulator-fixed"; |
| 28 | + regulator-name = "VREG_1P8"; |
| 29 | + |
| 30 | + regulator-min-microvolt = <1800000>; |
| 31 | + regulator-max-microvolt = <1800000>; |
| 32 | + regulator-always-on; |
| 33 | + regulator-boot-on; |
| 34 | + |
| 35 | + vin-supply = <&vreg_4p2>; |
| 36 | + }; |
| 37 | + |
| 38 | + vreg_3p3: regulator-vreg-3p3 { |
| 39 | + compatible = "regulator-fixed"; |
| 40 | + regulator-name = "VREG_3P3"; |
| 41 | + |
| 42 | + regulator-min-microvolt = <3300000>; |
| 43 | + regulator-max-microvolt = <3300000>; |
| 44 | + regulator-always-on; |
| 45 | + regulator-boot-on; |
| 46 | + |
| 47 | + vin-supply = <&vreg_4p2>; |
| 48 | + }; |
| 49 | + |
| 50 | + vreg_4p2: regulator-vreg-4p2 { |
| 51 | + compatible = "regulator-fixed"; |
| 52 | + regulator-name = "VREG_4P2"; |
| 53 | + |
| 54 | + regulator-min-microvolt = <4200000>; |
| 55 | + regulator-max-microvolt = <4200000>; |
| 56 | + regulator-always-on; |
| 57 | + regulator-boot-on; |
| 58 | + |
| 59 | + vin-supply = <&vreg_sys_pwr>; |
| 60 | + }; |
| 61 | + |
| 62 | + vreg_sys_pwr: regulator-vreg-sys-pwr { |
| 63 | + compatible = "regulator-fixed"; |
| 64 | + regulator-name = "VREG_SYS_PWR"; |
| 65 | + |
| 66 | + regulator-min-microvolt = <24000000>; |
| 67 | + regulator-max-microvolt = <24000000>; |
| 68 | + regulator-always-on; |
| 69 | + regulator-boot-on; |
| 70 | + }; |
| 71 | +}; |
| 72 | + |
| 73 | +ðernet1 { |
| 74 | + phy-handle = <&hsgmii_phy1>; |
| 75 | + phy-mode = "2500base-x"; |
| 76 | + |
| 77 | + pinctrl-0 = <ðernet1_default>; |
| 78 | + pinctrl-names = "default"; |
| 79 | + |
| 80 | + snps,mtl-rx-config = <&mtl_rx_setup1>; |
| 81 | + snps,mtl-tx-config = <&mtl_tx_setup1>; |
| 82 | + |
| 83 | + nvmem-cells = <&mac_addr1>; |
| 84 | + nvmem-cell-names = "mac-address"; |
| 85 | + |
| 86 | + status = "okay"; |
| 87 | + |
| 88 | + mdio { |
| 89 | + compatible = "snps,dwmac-mdio"; |
| 90 | + #address-cells = <1>; |
| 91 | + #size-cells = <0>; |
| 92 | + |
| 93 | + hsgmii_phy1: ethernet-phy@18 { |
| 94 | + compatible = "ethernet-phy-id004d.d101"; |
| 95 | + reg = <0x18>; |
| 96 | + reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>; |
| 97 | + reset-assert-us = <11000>; |
| 98 | + reset-deassert-us = <70000>; |
| 99 | + }; |
| 100 | + }; |
| 101 | + |
| 102 | + mtl_rx_setup1: rx-queues-config { |
| 103 | + snps,rx-queues-to-use = <4>; |
| 104 | + snps,rx-sched-sp; |
| 105 | + |
| 106 | + queue0 { |
| 107 | + snps,dcb-algorithm; |
| 108 | + snps,map-to-dma-channel = <0x0>; |
| 109 | + snps,route-up; |
| 110 | + snps,priority = <0x1>; |
| 111 | + }; |
| 112 | + |
| 113 | + queue1 { |
| 114 | + snps,dcb-algorithm; |
| 115 | + snps,map-to-dma-channel = <0x1>; |
| 116 | + snps,route-ptp; |
| 117 | + }; |
| 118 | + |
| 119 | + queue2 { |
| 120 | + snps,avb-algorithm; |
| 121 | + snps,map-to-dma-channel = <0x2>; |
| 122 | + snps,route-avcp; |
| 123 | + }; |
| 124 | + |
| 125 | + queue3 { |
| 126 | + snps,avb-algorithm; |
| 127 | + snps,map-to-dma-channel = <0x3>; |
| 128 | + snps,priority = <0xc>; |
| 129 | + }; |
| 130 | + }; |
| 131 | + |
| 132 | + mtl_tx_setup1: tx-queues-config { |
| 133 | + snps,tx-queues-to-use = <4>; |
| 134 | + |
| 135 | + queue0 { |
| 136 | + snps,dcb-algorithm; |
| 137 | + }; |
| 138 | + |
| 139 | + queue1 { |
| 140 | + snps,dcb-algorithm; |
| 141 | + }; |
| 142 | + |
| 143 | + queue2 { |
| 144 | + snps,avb-algorithm; |
| 145 | + snps,send_slope = <0x1000>; |
| 146 | + snps,idle_slope = <0x1000>; |
| 147 | + snps,high_credit = <0x3e800>; |
| 148 | + snps,low_credit = <0xffc18000>; |
| 149 | + }; |
| 150 | + |
| 151 | + queue3 { |
| 152 | + snps,avb-algorithm; |
| 153 | + snps,send_slope = <0x1000>; |
| 154 | + snps,idle_slope = <0x1000>; |
| 155 | + snps,high_credit = <0x3e800>; |
| 156 | + snps,low_credit = <0xffc18000>; |
| 157 | + }; |
| 158 | + }; |
| 159 | +}; |
| 160 | + |
| 161 | +&i2c18 { |
| 162 | + #address-cells = <1>; |
| 163 | + #size-cells = <0>; |
| 164 | + |
| 165 | + eeprom@52 { |
| 166 | + compatible = "giantec,gt24c256c", "atmel,24c256"; |
| 167 | + reg = <0x52>; |
| 168 | + pagesize = <64>; |
| 169 | + |
| 170 | + nvmem-layout { |
| 171 | + compatible = "fixed-layout"; |
| 172 | + #address-cells = <1>; |
| 173 | + #size-cells = <1>; |
| 174 | + |
| 175 | + mac_addr1: mac-addr@0 { |
| 176 | + reg = <0x0 0x6>; |
| 177 | + }; |
| 178 | + }; |
| 179 | + }; |
| 180 | +}; |
| 181 | + |
| 182 | +&pcie0 { |
| 183 | + iommu-map = <0x0 &pcie_smmu 0x0 0x1>, |
| 184 | + <0x100 &pcie_smmu 0x1 0x1>, |
| 185 | + <0x208 &pcie_smmu 0x2 0x1>, |
| 186 | + <0x210 &pcie_smmu 0x3 0x1>, |
| 187 | + <0x218 &pcie_smmu 0x4 0x1>, |
| 188 | + <0x300 &pcie_smmu 0x5 0x1>, |
| 189 | + <0x400 &pcie_smmu 0x6 0x1>, |
| 190 | + <0x500 &pcie_smmu 0x7 0x1>, |
| 191 | + <0x501 &pcie_smmu 0x8 0x1>; |
| 192 | +}; |
| 193 | + |
| 194 | +&pcieport0 { |
| 195 | + #address-cells = <3>; |
| 196 | + #size-cells = <2>; |
| 197 | + |
| 198 | + pcie@0,0 { |
| 199 | + compatible = "pci1179,0623"; |
| 200 | + reg = <0x10000 0x0 0x0 0x0 0x0>; |
| 201 | + #address-cells = <3>; |
| 202 | + #size-cells = <2>; |
| 203 | + |
| 204 | + device_type = "pci"; |
| 205 | + ranges; |
| 206 | + bus-range = <0x2 0xff>; |
| 207 | + |
| 208 | + vddc-supply = <&vreg_0p9>; |
| 209 | + vdd18-supply = <&vreg_1p8>; |
| 210 | + vdd09-supply = <&vreg_0p9>; |
| 211 | + vddio1-supply = <&vreg_1p8>; |
| 212 | + vddio2-supply = <&vreg_1p8>; |
| 213 | + vddio18-supply = <&vreg_1p8>; |
| 214 | + |
| 215 | + i2c-parent = <&i2c18 0x77>; |
| 216 | + |
| 217 | + resx-gpios = <&tlmm 140 GPIO_ACTIVE_LOW>; |
| 218 | + |
| 219 | + pinctrl-0 = <&tc9563_resx_n>; |
| 220 | + pinctrl-names = "default"; |
| 221 | + |
| 222 | + pcie@1,0 { |
| 223 | + reg = <0x20800 0x0 0x0 0x0 0x0>; |
| 224 | + #address-cells = <3>; |
| 225 | + #size-cells = <2>; |
| 226 | + |
| 227 | + device_type = "pci"; |
| 228 | + ranges; |
| 229 | + bus-range = <0x3 0xff>; |
| 230 | + }; |
| 231 | + |
| 232 | + pcie@2,0 { |
| 233 | + reg = <0x21000 0x0 0x0 0x0 0x0>; |
| 234 | + #address-cells = <3>; |
| 235 | + #size-cells = <2>; |
| 236 | + |
| 237 | + device_type = "pci"; |
| 238 | + ranges; |
| 239 | + bus-range = <0x4 0xff>; |
| 240 | + }; |
| 241 | + |
| 242 | + pcie@3,0 { |
| 243 | + reg = <0x21800 0x0 0x0 0x0 0x0>; |
| 244 | + #address-cells = <3>; |
| 245 | + #size-cells = <2>; |
| 246 | + device_type = "pci"; |
| 247 | + ranges; |
| 248 | + bus-range = <0x5 0xff>; |
| 249 | + |
| 250 | + pci@0,0 { |
| 251 | + reg = <0x50000 0x0 0x0 0x0 0x0>; |
| 252 | + #address-cells = <3>; |
| 253 | + #size-cells = <2>; |
| 254 | + device_type = "pci"; |
| 255 | + ranges; |
| 256 | + }; |
| 257 | + |
| 258 | + pci@0,1 { |
| 259 | + reg = <0x50100 0x0 0x0 0x0 0x0>; |
| 260 | + #address-cells = <3>; |
| 261 | + #size-cells = <2>; |
| 262 | + device_type = "pci"; |
| 263 | + ranges; |
| 264 | + }; |
| 265 | + }; |
| 266 | + }; |
| 267 | +}; |
| 268 | + |
| 269 | +&serdes1 { |
| 270 | + phy-supply = <&vreg_l5a>; |
| 271 | + |
| 272 | + status = "okay"; |
| 273 | +}; |
| 274 | + |
| 275 | +&tlmm { |
| 276 | + ethernet1_default: ethernet1-default-state { |
| 277 | + ethernet1-mdc-pins { |
| 278 | + pins = "gpio20"; |
| 279 | + function = "emac1_mdc"; |
| 280 | + drive-strength = <16>; |
| 281 | + bias-pull-up; |
| 282 | + }; |
| 283 | + |
| 284 | + ethernet1-mdio-pins { |
| 285 | + pins = "gpio21"; |
| 286 | + function = "emac1_mdio"; |
| 287 | + drive-strength = <16>; |
| 288 | + bias-pull-up; |
| 289 | + }; |
| 290 | + }; |
| 291 | + |
| 292 | + tc9563_resx_n: tc9563-resx-state { |
| 293 | + pins = "gpio140"; |
| 294 | + function = "gpio"; |
| 295 | + |
| 296 | + bias-disable; |
| 297 | + input-disable; |
| 298 | + output-enable; |
| 299 | + power-source = <0>; |
| 300 | + }; |
| 301 | +}; |
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