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1 | 1 | // SPDX-License-Identifier: BSD-3-Clause |
2 | 2 | /* |
3 | | - * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. |
| 3 | + * Copyright (c) 2024-2025, Qualcomm Innovation Center, Inc. All rights reserved. |
4 | 4 | */ |
5 | 5 | /dts-v1/; |
6 | 6 |
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|
211 | 211 | }; |
212 | 212 | }; |
213 | 213 |
|
| 214 | +ðernet { |
| 215 | + pinctrl-0 = <ðernet_defaults>; |
| 216 | + pinctrl-names = "default"; |
| 217 | + |
| 218 | + phy-handle = <&rgmii_phy>; |
| 219 | + phy-mode = "rgmii-id"; |
| 220 | + qcom,rx-prog-swap; |
| 221 | + |
| 222 | + snps,mtl-rx-config = <&mtl_rx_setup>; |
| 223 | + snps,mtl-tx-config = <&mtl_tx_setup>; |
| 224 | + |
| 225 | + status = "okay"; |
| 226 | + |
| 227 | + mdio { |
| 228 | + compatible = "snps,dwmac-mdio"; |
| 229 | + #address-cells = <1>; |
| 230 | + #size-cells = <0>; |
| 231 | + |
| 232 | + rgmii_phy: phy@7 { |
| 233 | + compatible = "ethernet-phy-ieee802.3-c22"; |
| 234 | + reg = <0x7>; |
| 235 | + |
| 236 | + interrupts-extended = <&tlmm 121 IRQ_TYPE_EDGE_FALLING>; |
| 237 | + device_type = "ethernet-phy"; |
| 238 | + reset-gpios = <&tlmm 104 GPIO_ACTIVE_LOW>; |
| 239 | + reset-assert-us = <11000>; |
| 240 | + reset-deassert-us = <70000>; |
| 241 | + }; |
| 242 | + }; |
| 243 | + |
| 244 | + mtl_rx_setup: rx-queues-config { |
| 245 | + snps,rx-queues-to-use = <1>; |
| 246 | + snps,rx-sched-sp; |
| 247 | + |
| 248 | + queue0 { |
| 249 | + snps,dcb-algorithm; |
| 250 | + snps,map-to-dma-channel = <0x0>; |
| 251 | + snps,route-up; |
| 252 | + snps,priority = <0x1>; |
| 253 | + }; |
| 254 | + }; |
| 255 | + |
| 256 | + mtl_tx_setup: tx-queues-config { |
| 257 | + snps,tx-queues-to-use = <1>; |
| 258 | + snps,tx-sched-wrr; |
| 259 | + |
| 260 | + queue0 { |
| 261 | + snps,weight = <0x10>; |
| 262 | + snps,dcb-algorithm; |
| 263 | + snps,priority = <0x0>; |
| 264 | + }; |
| 265 | + }; |
| 266 | +}; |
| 267 | + |
214 | 268 | &gcc { |
215 | 269 | clocks = <&rpmhcc RPMH_CXO_CLK>, |
216 | 270 | <&rpmhcc RPMH_CXO_CLK_A>, |
217 | 271 | <&sleep_clk>; |
218 | 272 | }; |
219 | 273 |
|
| 274 | +&pcie { |
| 275 | + perst-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>; |
| 276 | + wake-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; |
| 277 | + |
| 278 | + pinctrl-0 = <&pcie_default_state>; |
| 279 | + pinctrl-names = "default"; |
| 280 | + |
| 281 | + status = "okay"; |
| 282 | +}; |
| 283 | + |
| 284 | +&pcie_phy { |
| 285 | + vdda-phy-supply = <&vreg_l5a>; |
| 286 | + vdda-pll-supply = <&vreg_l12a>; |
| 287 | + |
| 288 | + status = "okay"; |
| 289 | +}; |
| 290 | + |
220 | 291 | &pm8150_gpios { |
221 | 292 | usb2_en: usb2-en-state { |
222 | 293 | pins = "gpio10"; |
|
240 | 311 | status = "okay"; |
241 | 312 | }; |
242 | 313 |
|
| 314 | +&remoteproc_adsp { |
| 315 | + firmware-name = "qcom/qcs615/adsp.mbn"; |
| 316 | + |
| 317 | + status = "okay"; |
| 318 | +}; |
| 319 | + |
| 320 | +&remoteproc_cdsp { |
| 321 | + firmware-name = "qcom/qcs615/cdsp.mbn"; |
| 322 | + |
| 323 | + status = "okay"; |
| 324 | +}; |
| 325 | + |
243 | 326 | &rpmhcc { |
244 | 327 | clocks = <&xo_board_clk>; |
245 | 328 | }; |
|
278 | 361 | status = "okay"; |
279 | 362 | }; |
280 | 363 |
|
| 364 | +&tlmm { |
| 365 | + ethernet_defaults: ethernet-defaults-state { |
| 366 | + mdc-pins { |
| 367 | + pins = "gpio113"; |
| 368 | + function = "rgmii"; |
| 369 | + bias-pull-up; |
| 370 | + }; |
| 371 | + |
| 372 | + mdio-pins { |
| 373 | + pins = "gpio114"; |
| 374 | + function = "rgmii"; |
| 375 | + bias-pull-up; |
| 376 | + }; |
| 377 | + |
| 378 | + rgmii-rx-pins { |
| 379 | + pins = "gpio81", "gpio82", "gpio83", "gpio102", "gpio103", "gpio112"; |
| 380 | + function = "rgmii"; |
| 381 | + bias-disable; |
| 382 | + drive-strength = <2>; |
| 383 | + }; |
| 384 | + |
| 385 | + rgmii-tx-pins { |
| 386 | + pins = "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97"; |
| 387 | + function = "rgmii"; |
| 388 | + bias-pull-up; |
| 389 | + drive-strength = <16>; |
| 390 | + }; |
| 391 | + |
| 392 | + phy-intr-pins { |
| 393 | + pins = "gpio121"; |
| 394 | + function = "gpio"; |
| 395 | + bias-disable; |
| 396 | + drive-strength = <8>; |
| 397 | + }; |
| 398 | + |
| 399 | + phy-reset-pins { |
| 400 | + pins = "gpio104"; |
| 401 | + function = "gpio"; |
| 402 | + bias-pull-up; |
| 403 | + drive-strength = <16>; |
| 404 | + }; |
| 405 | + |
| 406 | + pps-pins { |
| 407 | + pins = "gpio91"; |
| 408 | + function = "rgmii"; |
| 409 | + bias-disable; |
| 410 | + drive-strength = <8>; |
| 411 | + }; |
| 412 | + }; |
| 413 | + |
| 414 | + pcie_default_state: pcie-default-state { |
| 415 | + clkreq-pins { |
| 416 | + pins = "gpio90"; |
| 417 | + function = "pcie_clk_req"; |
| 418 | + drive-strength = <2>; |
| 419 | + bias-pull-up; |
| 420 | + }; |
| 421 | + |
| 422 | + perst-pins { |
| 423 | + pins = "gpio101"; |
| 424 | + function = "gpio"; |
| 425 | + drive-strength = <2>; |
| 426 | + bias-pull-down; |
| 427 | + }; |
| 428 | + |
| 429 | + wake-pins { |
| 430 | + pins = "gpio100"; |
| 431 | + function = "gpio"; |
| 432 | + drive-strength = <2>; |
| 433 | + bias-pull-up; |
| 434 | + }; |
| 435 | + }; |
| 436 | +}; |
| 437 | + |
281 | 438 | &uart0 { |
282 | 439 | status = "okay"; |
283 | 440 | }; |
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