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Krishna chaitanya chundruquic-tingweiz
Krishna chaitanya chundru
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quic-tingweiz
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FORMLIST: arm64: dts: qcom: qcs615: enable pcie
Add configurations in devicetree for PCIe0, including registers, clocks, interrupts and phy setting sequence. Add PCIe lane equalization preset properties for 8 GT/s. Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://lore.kernel.org/all/20250702103549.712039-3-ziyue.zhang@oss.qualcomm.com/
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‎arch/arm64/boot/dts/qcom/qcs615.dtsi‎

Lines changed: 138 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1100,6 +1100,144 @@
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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pcie: pcie@1c08000 {
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device_type = "pci";
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compatible = "qcom,pcie-qcs615", "qcom,pcie-sm8150";
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reg = <0x0 0x01c08000 0x0 0x3000>,
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<0x0 0x40000000 0x0 0xf1d>,
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<0x0 0x40000f20 0x0 0xa8>,
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<0x0 0x40001000 0x0 0x1000>,
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<0x0 0x40100000 0x0 0x100000>,
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<0x0 0x01c0b000 0x0 0x1000>;
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reg-names = "parf",
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"dbi",
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"elbi",
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"atu",
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"config",
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"mhi";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
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<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
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bus-range = <0x00 0xff>;
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dma-coherent;
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linux,pci-domain = <0>;
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num-lanes = <1>;
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interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi0",
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"msi1",
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"msi2",
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"msi3",
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"msi4",
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"msi5",
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"msi6",
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"msi7",
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"global";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
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<&gcc GCC_PCIE_0_AUX_CLK>,
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<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
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clock-names = "pipe",
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"aux",
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"cfg",
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"bus_master",
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"bus_slave",
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"slave_q2a";
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assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
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assigned-clock-rates = <19200000>;
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interconnects = <&aggre1_noc MASTER_PCIE QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
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&config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
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interconnect-names = "pcie-mem", "cpu-pcie";
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iommu-map = <0x0 &apps_smmu 0x400 0x1>,
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<0x100 &apps_smmu 0x401 0x1>;
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resets = <&gcc GCC_PCIE_0_BCR>;
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reset-names = "pci";
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power-domains = <&gcc PCIE_0_GDSC>;
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phys = <&pcie_phy>;
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phy-names = "pciephy";
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max-link-speed = <2>;
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operating-points-v2 = <&pcie_opp_table>;
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status = "disabled";
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pcie_opp_table: opp-table {
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compatible = "operating-points-v2";
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1196+
/* GEN 1 x1 */
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opp-2500000 {
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opp-hz = /bits/ 64 <2500000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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opp-peak-kBps = <250000 1>;
1201+
};
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1203+
/* GEN 2 x1 */
1204+
opp-5000000 {
1205+
opp-hz = /bits/ 64 <5000000>;
1206+
required-opps = <&rpmhpd_opp_low_svs>;
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opp-peak-kBps = <500000 1>;
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};
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};
1210+
};
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1212+
pcie_phy: phy@1c0e000 {
1213+
compatible = "qcom,qcs615-qmp-gen3x1-pcie-phy";
1214+
reg = <0x0 0x01c0e000 0x0 0x1000>;
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clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
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<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_0_CLKREF_CLK>,
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<&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
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<&gcc GCC_PCIE_0_PIPE_CLK>;
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clock-names = "aux",
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"cfg_ahb",
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"ref",
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"refgen",
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"pipe";
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resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1228+
reset-names = "phy";
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assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
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assigned-clock-rates = <100000000>;
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#clock-cells = <0>;
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clock-output-names = "pcie_0_pipe_clk";
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#phy-cells = <0>;
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status = "disabled";
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};
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ufs_mem_hc: ufshc@1d84000 {
11041242
compatible = "qcom,qcs615-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
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reg = <0x0 0x01d84000 0x0 0x3000>,

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