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Vikash Garodiagouravk-qualcomm
Vikash Garodia
authored and
gouravk-qualcomm
committed
BACKPORT: media: iris: Move vpu register defines to common header file
Some of vpu4 register defines are common with vpu3x. Move those into the common register defines header. This is done to reuse the defines for vpu4 in subsequent patch which enables the power sequence for vpu4. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Co-developed-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com> Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Co-developed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Bryan O'Donoghue <bod@kernel.org> Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org> Link: https://lore.kernel.org/all/20251210-knp_video-v4-4-8d11d840358a@oss.qualcomm.com/ (cherry picked from commit 2fc9b85)
1 parent 1fbfb19 commit 422f3a6

3 files changed

Lines changed: 61 additions & 85 deletions

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‎drivers/media/platform/qcom/iris/iris_vpu3x.c‎

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@@ -11,48 +11,6 @@
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#include "iris_vpu_common.h"
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#include "iris_vpu_register_defines.h"
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14-
#define WRAPPER_TZ_BASE_OFFS 0x000C0000
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#define AON_BASE_OFFS 0x000E0000
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#define AON_MVP_NOC_RESET 0x0001F000
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18-
#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54)
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#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58)
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#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C)
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#define REQ_POWER_DOWN_PREP BIT(0)
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#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60)
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#define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is complete */
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#define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is denied */
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#define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */
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#define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88)
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#define CORE_CLK_RUN 0x0
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/* VPU v3.5 */
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#define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 (WRAPPER_BASE_OFFS + 0x78)
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31-
#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14)
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#define CTL_AXI_CLK_HALT BIT(0)
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#define CTL_CLK_HALT BIT(1)
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#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18)
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#define RESET_HIGH BIT(0)
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38-
#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160)
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#define CORE_BRIDGE_SW_RESET BIT(0)
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#define CORE_BRIDGE_HW_RESET_DISABLE BIT(1)
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42-
#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168)
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#define MSK_SIGNAL_FROM_TENSILICA BIT(0)
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#define MSK_CORE_POWER_ON BIT(1)
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#define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000)
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#define VIDEO_NOC_RESET_REQ (BIT(0) | BIT(1))
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#define AON_WRAPPER_MVP_NOC_RESET_ACK (AON_MVP_NOC_RESET + 0x004)
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#define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70)
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#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS)
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#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4)
55-
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#define AON_WRAPPER_MVP_NOC_CORE_SW_RESET (AON_BASE_OFFS + 0x18)
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#define SW_RESET BIT(0)
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#define AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL (AON_BASE_OFFS + 0x20)

‎drivers/media/platform/qcom/iris/iris_vpu_common.c‎

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#include "iris_vpu_common.h"
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#include "iris_vpu_register_defines.h"
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#define WRAPPER_TZ_BASE_OFFS 0x000C0000
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#define AON_BASE_OFFS 0x000E0000
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#define CPU_IC_BASE_OFFS (CPU_BASE_OFFS)
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#define CPU_CS_A2HSOFTINTCLR (CPU_CS_BASE_OFFS + 0x1C)
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#define CLEAR_XTENSA2HOST_INTR BIT(0)
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#define CTRL_INIT (CPU_CS_BASE_OFFS + 0x48)
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#define CTRL_STATUS (CPU_CS_BASE_OFFS + 0x4C)
@@ -35,42 +28,6 @@
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#define UC_REGION_ADDR (CPU_CS_BASE_OFFS + 0x64)
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#define UC_REGION_SIZE (CPU_CS_BASE_OFFS + 0x68)
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#define CPU_CS_H2XSOFTINTEN (CPU_CS_BASE_OFFS + 0x148)
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#define HOST2XTENSA_INTR_ENABLE BIT(0)
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#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168)
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#define MSK_SIGNAL_FROM_TENSILICA BIT(0)
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#define MSK_CORE_POWER_ON BIT(1)
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#define CPU_IC_SOFTINT (CPU_IC_BASE_OFFS + 0x150)
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#define CPU_IC_SOFTINT_H2A_SHFT 0x0
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#define WRAPPER_INTR_STATUS (WRAPPER_BASE_OFFS + 0x0C)
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#define WRAPPER_INTR_STATUS_A2HWD_BMSK BIT(3)
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#define WRAPPER_INTR_STATUS_A2H_BMSK BIT(2)
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#define WRAPPER_INTR_MASK (WRAPPER_BASE_OFFS + 0x10)
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#define WRAPPER_INTR_MASK_A2HWD_BMSK BIT(3)
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#define WRAPPER_INTR_MASK_A2HCPU_BMSK BIT(2)
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#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54)
57-
#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58)
58-
#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C)
59-
#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60)
60-
61-
#define WRAPPER_TZ_CPU_STATUS (WRAPPER_TZ_BASE_OFFS + 0x10)
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#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14)
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#define CTL_AXI_CLK_HALT BIT(0)
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#define CTL_CLK_HALT BIT(1)
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#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18)
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#define RESET_HIGH BIT(0)
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#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS)
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#define REQ_POWER_DOWN_PREP BIT(0)
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#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4)
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static void iris_vpu_interrupt_init(struct iris_core *core)
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{
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u32 mask_val;

‎drivers/media/platform/qcom/iris/iris_vpu_register_defines.h‎

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#define __IRIS_VPU_REGISTER_DEFINES_H__
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#define VCODEC_BASE_OFFS 0x00000000
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#define AON_MVP_NOC_RESET 0x0001F000
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#define CPU_BASE_OFFS 0x000A0000
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#define WRAPPER_BASE_OFFS 0x000B0000
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#define WRAPPER_TZ_BASE_OFFS 0x000C0000
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#define AON_BASE_OFFS 0x000E0000
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#define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70)
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#define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000)
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#define VIDEO_NOC_RESET_REQ (BIT(0) | BIT(1))
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#define AON_WRAPPER_MVP_NOC_RESET_ACK (AON_MVP_NOC_RESET + 0x004)
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#define CPU_CS_BASE_OFFS (CPU_BASE_OFFS)
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#define CPU_IC_BASE_OFFS (CPU_BASE_OFFS)
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#define CPU_CS_A2HSOFTINTCLR (CPU_CS_BASE_OFFS + 0x1C)
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#define CLEAR_XTENSA2HOST_INTR BIT(0)
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#define CPU_CS_H2XSOFTINTEN (CPU_CS_BASE_OFFS + 0x148)
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#define HOST2XTENSA_INTR_ENABLE BIT(0)
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32+
#define CPU_IC_SOFTINT (CPU_IC_BASE_OFFS + 0x150)
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#define CPU_IC_SOFTINT_H2A_SHFT 0x0
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#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160)
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#define CORE_BRIDGE_SW_RESET BIT(0)
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#define CORE_BRIDGE_HW_RESET_DISABLE BIT(1)
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#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168)
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#define MSK_SIGNAL_FROM_TENSILICA BIT(0)
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#define MSK_CORE_POWER_ON BIT(1)
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43+
#define WRAPPER_INTR_STATUS (WRAPPER_BASE_OFFS + 0x0C)
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#define WRAPPER_INTR_STATUS_A2HWD_BMSK BIT(3)
45+
#define WRAPPER_INTR_STATUS_A2H_BMSK BIT(2)
46+
47+
#define WRAPPER_INTR_MASK (WRAPPER_BASE_OFFS + 0x10)
48+
#define WRAPPER_INTR_MASK_A2HWD_BMSK BIT(3)
49+
#define WRAPPER_INTR_MASK_A2HCPU_BMSK BIT(2)
50+
51+
#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54)
52+
#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58)
53+
#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C)
54+
#define REQ_POWER_DOWN_PREP BIT(0)
55+
56+
#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60)
57+
#define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is complete */
58+
#define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is denied */
59+
#define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */
60+
61+
#define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 (WRAPPER_BASE_OFFS + 0x78)
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#define WRAPPER_CORE_POWER_STATUS (WRAPPER_BASE_OFFS + 0x80)
63+
#define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88)
64+
#define CORE_CLK_RUN 0x0
65+
66+
#define WRAPPER_TZ_CPU_STATUS (WRAPPER_TZ_BASE_OFFS + 0x10)
67+
68+
#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14)
69+
#define CTL_AXI_CLK_HALT BIT(0)
70+
#define CTL_CLK_HALT BIT(1)
71+
72+
#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18)
73+
#define RESET_HIGH BIT(0)
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75+
#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS)
76+
#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4)
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#endif

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