Commit 3caa15b
FROMLIST: cpuidle: Deny idle entry when CPU already have IPI interrupt pending
CPU can get IPI interrupt from another CPU while it is executing
cpuidle_select() or about to execute same. The selection do not account
for pending interrupts and may continue to enter selected idle state only
to exit immediately.
Example trace collected when there is cross CPU IPI.
[000] 154.892148: sched_waking: comm=sugov:4 pid=491 prio=-1 target_cpu=007
[000] 154.892148: ipi_raise: target_mask=00000000,00000080 (Function call interrupts)
[007] 154.892162: cpu_idle: state=2 cpu_id=7
[007] 154.892208: cpu_idle: state=4294967295 cpu_id=7
[007] 154.892211: irq_handler_entry: irq=2 name=IPI
[007] 154.892211: ipi_entry: (Function call interrupts)
[007] 154.892213: sched_wakeup: comm=sugov:4 pid=491 prio=-1 target_cpu=007
[007] 154.892214: ipi_exit: (Function call interrupts)
This impacts performance and the above count increments.
commit ccde652 ("smp: Introduce a helper function to check for pending
IPIs") already introduced a helper function to check the pending IPIs and
it is used in pmdomain governor to deny the cluster level idle state when
there is a pending IPI on any of cluster CPUs.
This however does not stop CPU to enter CPU level idle state. Make use of
same at CPUidle to deny the idle entry when there is already IPI pending.
With change observing glmark2 [1] off screen scores improving in the range
of 25% to 30% on Qualcomm lemans-evk board which is arm64 based having two
clusters each with 4 CPUs.
[1] https://github.com/glmark2/glmark2
Link: https://lore.kernel.org/r/20260403-cpuidle_ipi-v2-1-b3e44b032e2c@oss.qualcomm.com
Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com>
Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com>1 parent b524234 commit 3caa15b
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