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1911 | 1911 | clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>; |
1912 | 1912 | clock-names = "core"; |
1913 | 1913 |
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1914 | | - interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; |
| 1914 | + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>; |
1915 | 1915 |
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1916 | 1916 | interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS |
1917 | 1917 | &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; |
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1987 | 1987 | power-domain-names = "cx", |
1988 | 1988 | "gx"; |
1989 | 1989 |
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1990 | | - interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, |
1991 | | - <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; |
| 1990 | + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>, |
| 1991 | + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>; |
1992 | 1992 | interrupt-names = "oob", |
1993 | 1993 | "gmu"; |
1994 | 1994 |
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2023 | 2023 | reg = <0x0 0x050a0000 0x0 0x40000>; |
2024 | 2024 | #iommu-cells = <2>; |
2025 | 2025 | #global-interrupts = <1>; |
2026 | | - interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, |
2027 | | - <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, |
2028 | | - <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, |
2029 | | - <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, |
2030 | | - <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, |
2031 | | - <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, |
2032 | | - <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, |
2033 | | - <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, |
2034 | | - <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; |
| 2026 | + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>, |
| 2027 | + <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH 0>, |
| 2028 | + <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH 0>, |
| 2029 | + <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>, |
| 2030 | + <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH 0>, |
| 2031 | + <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>, |
| 2032 | + <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH 0>, |
| 2033 | + <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH 0>, |
| 2034 | + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>; |
2035 | 2035 | clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, |
2036 | 2036 | <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, |
2037 | 2037 | <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; |
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