|
591 | 591 | }; |
592 | 592 |
|
593 | 593 | &gcc { |
594 | | - protected-clocks = <GCC_AGGRE_NOC_PCIE_1_AXI_CLK> ,<GCC_PCIE_1_AUX_CLK>, |
595 | | - <GCC_PCIE_1_AUX_CLK_SRC>, <GCC_PCIE_1_CFG_AHB_CLK>, |
596 | | - <GCC_PCIE_1_MSTR_AXI_CLK>, <GCC_PCIE_1_PHY_RCHNG_CLK_SRC>, |
597 | | - <GCC_PCIE_1_PIPE_CLK>, <GCC_PCIE_1_PIPE_CLK_SRC>, |
598 | | - <GCC_PCIE_1_SLV_AXI_CLK>, <GCC_PCIE_1_SLV_Q2A_AXI_CLK>, |
599 | | - <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, <GCC_QSPI_CORE_CLK>, |
| 594 | + protected-clocks = <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, <GCC_QSPI_CORE_CLK>, |
600 | 595 | <GCC_QSPI_CORE_CLK_SRC>,<GCC_USB30_SEC_MASTER_CLK>, |
601 | 596 | <GCC_USB30_SEC_MASTER_CLK_SRC>, <GCC_USB30_SEC_MOCK_UTMI_CLK>, |
602 | 597 | <GCC_USB30_SEC_MOCK_UTMI_CLK_SRC>, |
|
673 | 668 | status = "okay"; |
674 | 669 | }; |
675 | 670 |
|
| 671 | +&pcie1 { |
| 672 | + perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; |
| 673 | + |
| 674 | + pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>; |
| 675 | + pinctrl-names = "default"; |
| 676 | + |
| 677 | + status = "okay"; |
| 678 | +}; |
| 679 | + |
| 680 | +&pcie1_phy { |
| 681 | + vdda-phy-supply = <&vreg_l10c_0p88>; |
| 682 | + vdda-pll-supply = <&vreg_l6b_1p2>; |
| 683 | + |
| 684 | + status = "okay"; |
| 685 | +}; |
| 686 | + |
676 | 687 | &pm7250b_gpios { |
677 | 688 | lcd_disp_bias_en: lcd-disp-bias-en-state { |
678 | 689 | pins = "gpio2"; |
|
1071 | 1082 | bias-pull-up; |
1072 | 1083 | }; |
1073 | 1084 |
|
| 1085 | + pcie1_reset_n: pcie1-reset-n-state { |
| 1086 | + pins = "gpio2"; |
| 1087 | + function = "gpio"; |
| 1088 | + drive-strength = <16>; |
| 1089 | + output-low; |
| 1090 | + bias-disable; |
| 1091 | + }; |
| 1092 | + |
| 1093 | + pcie1_wake_n: pcie1-wake-n-state { |
| 1094 | + pins = "gpio3"; |
| 1095 | + function = "gpio"; |
| 1096 | + drive-strength = <2>; |
| 1097 | + bias-pull-up; |
| 1098 | + }; |
| 1099 | + |
| 1100 | + |
1074 | 1101 | sd_cd: sd-cd-state { |
1075 | 1102 | pins = "gpio91"; |
1076 | 1103 | function = "gpio"; |
|
0 commit comments