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rlaggyshKomal-Bajaj
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arm64: dts: msm: add interconnect devices for Shikra
Add interconnect devices for config_noc, system_noc, mc_virt, clk_virt, mem_noc, mmnrt_virt and mmrt_virt. This will allow consumers to get their path and set bandwidth constraints on them. Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
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arch/arm64/boot/dts/qcom/shikra.dtsi

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@@ -5,6 +5,8 @@
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/clock/qcom,shikra-gcc.h>
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#include <dt-bindings/interconnect/qcom,rpm-icc.h>
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#include <dt-bindings/interconnect/qcom,shikra.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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@@ -350,6 +352,14 @@
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};
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};
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mem_noc: interconnect@d00000 {
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compatible = "qcom,shikra-mem-noc-core";
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reg = <0x0 0x00d00000 0x0 0x43080>;
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clocks = <&gcc GCC_DDRSS_GPU_AXI_CLK>;
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clock-names = "gpu_axi";
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#interconnect-cells = <2>;
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};
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gcc: clock-controller@1400000 {
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compatible = "qcom,shikra-gcc";
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reg = <0x0 0x01400000 0x0 0x1f0000>;
@@ -366,6 +376,46 @@
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#power-domain-cells = <1>;
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};
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system_noc: interconnect@1880000 {
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compatible = "qcom,shikra-sys-noc";
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reg = <0x0 0x01880000 0x0 0x6a080>;
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clocks = <&gcc GCC_EMAC0_AXI_SYS_NOC_CLK>,
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<&gcc GCC_EMAC1_AXI_SYS_NOC_CLK>,
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<&gcc GCC_SYS_NOC_USB2_PRIM_AXI_CLK>,
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<&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>;
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clock-names = "emac0_axi",
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"emac1_axi",
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"usb2_axi",
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"usb3_axi";
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#interconnect-cells = <2>;
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clk_virt: interconnect-clk {
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compatible = "qcom,shikra-clk-virt";
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#interconnect-cells = <2>;
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};
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mc_virt: interconnect-mc {
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compatible = "qcom,shikra-mc-virt";
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#interconnect-cells = <2>;
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};
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mmrt_virt: interconnect-mmrt {
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compatible = "qcom,shikra-mmrt-virt";
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#interconnect-cells = <2>;
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};
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mmnrt_virt: interconnect-mmnrt {
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compatible = "qcom,shikra-mmnrt-virt";
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#interconnect-cells = <2>;
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};
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};
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config_noc: interconnect@1900000 {
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compatible = "qcom,shikra-config-noc";
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reg = <0x0 0x01900000 0x0 0x8080>;
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#interconnect-cells = <2>;
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};
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qfprom: efuse@1b44000 {
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compatible = "qcom,shikra-qfprom", "qcom,qfprom";
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reg = <0x0 0x01b44000 0x0 0x3000>;

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