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arm64: dts: qcom: Add QUPv3 UART console node for shikra
Enable console support for shikra. Signed-off-by: Xueyao An <xueyao.an@oss.qualcomm.com>
1 parent 646fe46 commit 74255bb

4 files changed

Lines changed: 52 additions & 1 deletion

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arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts

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chassis-type = "embedded";
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aliases {
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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&uart0 {
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status = "okay";
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};

arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts

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chassis-type = "embedded";
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aliases {
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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&uart0 {
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status = "okay";
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};

arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts

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chassis-type = "embedded";
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aliases {
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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&uart0 {
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status = "okay";
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};

arch/arm64/boot/dts/qcom/shikra.dtsi

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qup_uart0_default: qup-uart0-default-state {
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pins = "gpio0", "gpio1";
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function = "qup0_se1";
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function = "qup0_se0";
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drive-strength = <2>;
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bias-disable;
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};
@@ -677,6 +677,42 @@
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status = "disabled";
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};
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};
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qupv3_0: geniqup@4ac0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x0 0x04ac0000 0x0 0x2000>;
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clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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clock-names = "m-ahb",
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"s-ahb";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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uart0: serial@4a80000 {
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compatible = "qcom,geni-debug-uart";
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reg = <0x0 0x04a80000 0x0 0x4000>;
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interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
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clock-names = "se";
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interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
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&clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
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<&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
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&config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
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interconnect-names = "qup-core",
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"qup-config";
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pinctrl-0 = <&qup_uart0_default>;
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pinctrl-names = "default";
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status = "disabled";
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};
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};
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};
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timer {

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