From b7fa4e8942a7cf76b8579719ecc6eb0fe9e81351 Mon Sep 17 00:00:00 2001 From: Ramya! Date: Sat, 6 Jun 2026 22:57:42 +0530 Subject: [PATCH] add vlsi and embedded systems docs --- app/components/subjects.tsx | 2 +- app/sem7/vlsi/[chapter]/page.tsx | 144 +++++++++++++++++++++ app/sem7/vlsi/components/sidebar.tsx | 95 ++++++++++++++ app/sem7/vlsi/constants.ts | 17 +++ app/sem7/vlsi/content/chapter0.tsx | 138 ++++++++++++++++++++ app/sem7/vlsi/content/chapter1.tsx | 119 +++++++++++++++++ app/sem7/vlsi/content/chapter2.tsx | 94 ++++++++++++++ app/sem7/vlsi/content/chapter3.tsx | 90 +++++++++++++ app/sem7/vlsi/content/chapter4.tsx | 107 +++++++++++++++ app/sem7/vlsi/content/chapter5.tsx | 82 ++++++++++++ app/sem7/vlsi/content/chapter6.tsx | 81 ++++++++++++ app/sem7/vlsi/content/chapter7.tsx | 119 +++++++++++++++++ app/sem7/vlsi/content/chapter8.tsx | 89 +++++++++++++ app/sem7/vlsi/content/chapter9.tsx | 117 +++++++++++++++++ app/sem7/vlsi/layout.tsx | 23 ++++ app/sem7/vlsi/page.tsx | 5 + public/sem7/vlsi/embedded-system-stack.svg | 41 ++++++ public/sem7/vlsi/vlsi-design-flow.svg | 48 +++++++ 18 files changed, 1410 insertions(+), 1 deletion(-) create mode 100644 app/sem7/vlsi/[chapter]/page.tsx create mode 100644 app/sem7/vlsi/components/sidebar.tsx create mode 100644 app/sem7/vlsi/constants.ts create mode 100644 app/sem7/vlsi/content/chapter0.tsx create mode 100644 app/sem7/vlsi/content/chapter1.tsx create mode 100644 app/sem7/vlsi/content/chapter2.tsx create mode 100644 app/sem7/vlsi/content/chapter3.tsx create mode 100644 app/sem7/vlsi/content/chapter4.tsx create mode 100644 app/sem7/vlsi/content/chapter5.tsx create mode 100644 app/sem7/vlsi/content/chapter6.tsx create mode 100644 app/sem7/vlsi/content/chapter7.tsx create mode 100644 app/sem7/vlsi/content/chapter8.tsx create mode 100644 app/sem7/vlsi/content/chapter9.tsx create mode 100644 app/sem7/vlsi/layout.tsx create mode 100644 app/sem7/vlsi/page.tsx create mode 100644 public/sem7/vlsi/embedded-system-stack.svg create mode 100644 public/sem7/vlsi/vlsi-design-flow.svg diff --git a/app/components/subjects.tsx b/app/components/subjects.tsx index 724b848..74c85fd 100644 --- a/app/components/subjects.tsx +++ b/app/components/subjects.tsx @@ -125,7 +125,7 @@ const subjectCodes: Record = { }; // Available subjects -const available = ["ep", "c", "em1", "em2", "oops", "dsc", "coa", "os", "ml", "dops", "cd", "cle","ec"]; +const available = ["ep", "c", "em1", "em2", "oops", "dsc", "coa", "os", "ml", "dops", "cd", "cle", "ec", "vlsi"]; export default function SubjectsSection() { return ( diff --git a/app/sem7/vlsi/[chapter]/page.tsx b/app/sem7/vlsi/[chapter]/page.tsx new file mode 100644 index 0000000..536202c --- /dev/null +++ b/app/sem7/vlsi/[chapter]/page.tsx @@ -0,0 +1,144 @@ +import Link from "next/link"; +import { Metadata } from "next"; +import { Righteous } from "next/font/google"; +import { ArrowBigLeft, ArrowBigRight } from "lucide-react"; +import BookmarkButton from "../../../components/BookmarkButton"; +import { chapters } from "../constants"; +import { Ch0Content } from "../content/chapter0"; +import { Ch1Content } from "../content/chapter1"; +import { Ch2Content } from "../content/chapter2"; +import { Ch3Content } from "../content/chapter3"; +import { Ch4Content } from "../content/chapter4"; +import { Ch5Content } from "../content/chapter5"; +import { Ch6Content } from "../content/chapter6"; +import { Ch7Content } from "../content/chapter7"; +import { Ch8Content } from "../content/chapter8"; +import { Ch9Content } from "../content/chapter9"; + +const righteous = Righteous({ + subsets: ["latin"], + weight: "400", + variable: "--font-righteous", +}); + +const chapterComponents: Record = { + ch0: Ch0Content, + ch1: Ch1Content, + ch2: Ch2Content, + ch3: Ch3Content, + ch4: Ch4Content, + ch5: Ch5Content, + ch6: Ch6Content, + ch7: Ch7Content, + ch8: Ch8Content, + ch9: Ch9Content, +}; + +type ChapterProps = { + params: Promise<{ chapter: string }>; +}; + +export async function generateMetadata({ params }: ChapterProps): Promise { + const { chapter: chapterId } = await params; + const chapterData = chapters.find((chapter) => chapter.id === chapterId); + + return { + title: chapterData + ? `${chapterData.title} | VLSI and Embedded Systems | openCSE` + : "VLSI and Embedded Systems | openCSE", + }; +} + +export default async function ChapterPage({ params }: ChapterProps) { + const { chapter: chapterId } = await params; + const chapterData = chapters.find((chapter) => chapter.id === chapterId); + + if (!chapterData) { + return ( +
+

Chapter not found

+ + Return to Course Outline + +
+ ); + } + + const ChapterComponent = chapterComponents[chapterData.id]; + const currentIndex = chapters.findIndex((chapter) => chapter.id === chapterId); + const prevChapter = currentIndex > 0 ? chapters[currentIndex - 1] : null; + const nextChapter = currentIndex < chapters.length - 1 ? chapters[currentIndex + 1] : null; + + return ( +
+
+

+ VLSI and Embedded Systems +

+ +
+

{chapterData.title}

+ +
+ +
+ {prevChapter ? ( + + Previous + + ) : ( +
+ )} + + {nextChapter ? ( + + Next + + ) : ( +
+ )} +
+ +
+ +
+ +
+ {prevChapter ? ( + + {prevChapter.title} + + ) : ( +
+ )} + + {nextChapter ? ( + + {nextChapter.title} + + ) : ( +
+ )} +
+
+ ); +} diff --git a/app/sem7/vlsi/components/sidebar.tsx b/app/sem7/vlsi/components/sidebar.tsx new file mode 100644 index 0000000..1d792a2 --- /dev/null +++ b/app/sem7/vlsi/components/sidebar.tsx @@ -0,0 +1,95 @@ +"use client"; + +import { Righteous } from "next/font/google"; +import Link from "next/link"; +import { usePathname } from "next/navigation"; +import { useEffect, useState } from "react"; +import { chapters } from "../constants"; + +const righteous = Righteous({ + subsets: ["latin"], + weight: "400", + variable: "--font-righteous", +}); + +export default function Sidebar() { + const pathname = usePathname(); + const [open, setOpen] = useState(false); + + useEffect(() => { + if (window.innerWidth >= 768) { + setOpen(true); + } + }, []); + + return ( + <> +
setOpen(false)} + /> + +
+ + + +
+ + ); +} diff --git a/app/sem7/vlsi/constants.ts b/app/sem7/vlsi/constants.ts new file mode 100644 index 0000000..3a58890 --- /dev/null +++ b/app/sem7/vlsi/constants.ts @@ -0,0 +1,17 @@ +export type Chapter = { + id: string; + title: string; +}; + +export const chapters: Chapter[] = [ + { id: "ch0", title: "Course Outline" }, + { id: "ch1", title: "Introduction to VLSI" }, + { id: "ch2", title: "CMOS Technology" }, + { id: "ch3", title: "Digital IC Design" }, + { id: "ch4", title: "FPGA Basics" }, + { id: "ch5", title: "Embedded Systems Fundamentals" }, + { id: "ch6", title: "Microcontrollers and Processors" }, + { id: "ch7", title: "Arduino and Raspberry Pi Basics" }, + { id: "ch8", title: "Real-time Systems" }, + { id: "ch9", title: "Mini Projects and Resource Hub" }, +]; diff --git a/app/sem7/vlsi/content/chapter0.tsx b/app/sem7/vlsi/content/chapter0.tsx new file mode 100644 index 0000000..c4e9b26 --- /dev/null +++ b/app/sem7/vlsi/content/chapter0.tsx @@ -0,0 +1,138 @@ +export const Ch0Content = () => ( +
+

+ VLSI and Embedded Systems connects chip-level + design with real-world intelligent products. One part of the subject explains how + millions of transistors are organized into digital circuits, while the other part + explains how processors, sensors, firmware, and timing constraints work together + inside dedicated devices. +

+ +
+ +
+

Roadmap of the Module

+
+
+

VLSI Track

+
    +
  • Introduction to VLSI and design abstractions
    • +
  • CMOS technology and MOS transistor behavior
    • +
  • Digital IC design, timing, verification, and test
    • +
  • FPGA flow for rapid prototyping and RTL validation
    • +
+
+ +
+

Embedded Track

+
    +
  • Embedded system architecture and design constraints
    • +
  • Microcontrollers, processors, buses, timers, and interrupts
    • +
  • Arduino and Raspberry Pi for quick experimentation
    • +
  • Real-time scheduling, latency, jitter, and safety concerns
    • +
+
+
+
+ +
+ +
+

What You Should Learn From This Subject

+
    +
  • Read the basic vocabulary of chip design, firmware, and hardware interfaces.
    • +
  • Understand the difference between simulation, synthesis, implementation, and deployment.
    • +
  • Explain why power, area, delay, memory, and deadlines create trade-offs.
    • +
  • Connect theory to mini projects such as traffic-light controllers, sensor nodes, and FPGA prototypes.
    • +
+
+ +
+ +
+

Suggested Study Workflow

+
+
+ Step 1: Read the chapter concept and write + down the core terms such as CMOS, RTL, interrupt, deadline, and bitstream. +
+
+ Step 2: Solve one small example after each + topic. For example, trace a CMOS inverter, write a short Verilog module, or + blink an LED with a timer interrupt. +
+
+ Step 3: Use the resource links to watch one + lecture or run one practical exercise before moving to the next topic. +
+
+
+ +
+ +
+

Prerequisites

+
+
    +
  • Boolean algebra and basic digital logic gates
    • +
  • Elementary electronics, voltage, current, and semiconductor basics
    • +
  • Programming fundamentals in C or C++
    • +
  • Comfort with flowcharts, timing diagrams, and truth tables
    • +
+
+
+ +
+ +
+

Starter Resource Board

+
+ + +
+

Recommended Textbooks

+
    +
  • CMOS VLSI Design by Neil Weste and David Harris
    • +
  • Digital Integrated Circuits by Jan Rabaey
    • +
  • Embedded Systems by Raj Kamal
    • +
  • Embedded Systems: Real-Time Interfacing by Jonathan Valvano
    • +
+
+
+
+
+); diff --git a/app/sem7/vlsi/content/chapter1.tsx b/app/sem7/vlsi/content/chapter1.tsx new file mode 100644 index 0000000..3b49fec --- /dev/null +++ b/app/sem7/vlsi/content/chapter1.tsx @@ -0,0 +1,119 @@ +import Image from "next/image"; + +export const Ch1Content = () => ( +
+

+ Very Large Scale Integration means building + complex integrated circuits by placing a very large number of transistors on a + single silicon chip. Modern processors, mobile SoCs, memory devices, GPUs, and + network accelerators are all outcomes of VLSI design methodology. +

+ +
+ VLSI design flow from specification to silicon +

+ A compact view of the normal chip-design path: idea, RTL, verification, + synthesis, layout, and fabrication. +

+
+ +
+ +
+

Levels of Abstraction

+
    +
  • System level: what the chip must do and how it interacts with the full product.
    • +
  • Architectural level: datapath, control path, memory hierarchy, and bus structure.
    • +
  • RTL level: register transfers described using HDL such as Verilog or VHDL.
    • +
  • Gate level: logic gates, flip-flops, and netlists after synthesis.
    • +
  • Physical level: floorplanning, placement, routing, clock tree, and sign-off.
    • +
+
+ +
+ +
+

Front-end and Back-end Design

+
+ + + + + + + + + + + + + + + + + + + + +
StageFocusTypical Output
Front-endSpecification, RTL coding, simulation, functional verificationVerified HDL and constraints
Back-endSynthesis, placement, routing, timing closure, power checksLayout database and sign-off reports
+
+
+ +
+ +
+

Why VLSI Matters

+
    +
  • Higher functionality can be delivered in smaller area and lower cost per feature.
    • +
  • Shorter interconnections improve speed and help reduce board complexity.
    • +
  • Custom silicon enables domain-specific acceleration for AI, communication, and automotive systems.
    • +
  • Power-optimized chips are essential for battery devices and edge computing.
    • +
+
+ +
+

Practical Example

+
+

+ Imagine a smart door lock SoC. The specification may require keypad input, + Bluetooth communication, low power sleep mode, and secure authentication. + VLSI engineers break this into smaller hardware blocks such as GPIO, + state machines, timers, memory, and crypto accelerators before implementing + and verifying each block. +

+
+
+ +
+

Resource Links

+ +
+
+); diff --git a/app/sem7/vlsi/content/chapter2.tsx b/app/sem7/vlsi/content/chapter2.tsx new file mode 100644 index 0000000..f37a1f7 --- /dev/null +++ b/app/sem7/vlsi/content/chapter2.tsx @@ -0,0 +1,94 @@ +export const Ch2Content = () => ( +
+

+ CMOS, or Complementary Metal Oxide Semiconductor, + is the dominant technology used to build digital integrated circuits. It combines + NMOS and PMOS transistors so that one network pulls the output high while the other + pulls it low, enabling low static power and strong logic levels. +

+ +
+ +
+

Core Building Blocks

+
    +
  • NMOS transistor conducts well when the gate is high and helps pull the node toward ground.
    • +
  • PMOS transistor conducts well when the gate is low and helps pull the node toward VDD.
    • +
  • A CMOS inverter uses one PMOS and one NMOS to realize logical inversion.
    • +
  • Series and parallel transistor combinations build NAND, NOR, multiplexers, and transmission structures.
    • +
+
+ +
+ +
+

CMOS Inverter Operation

+
+ + + + + + + + + + + + + + + + + + + + + + + +
InputPMOSNMOSOutput
0ONOFF1
1OFFON0
+
+
+ Static power is ideally very low in CMOS because, in the steady state, one pull + network is OFF. Major power consumption appears during switching and leakage. +
+
+ +
+ +
+

Important Design Parameters

+
    +
  • Propagation delay: how long the output takes to respond to an input transition.
    • +
  • Noise margin: tolerance against unwanted voltage disturbance.
    • +
  • Fan-out: number of gate inputs driven by one output.
    • +
  • Dynamic power: approximately proportional to switching activity, capacitance, voltage squared, and frequency.
    • +
  • Leakage power: power consumed due to subthreshold and gate leakage paths.
    • +
+
+ +
+

Why Scaling Is Not Simple

+
+
    +
  • Lower dimensions increase density but make leakage and variability harder to control.
    • +
  • Interconnect delay becomes comparable to gate delay in deep submicron technologies.
    • +
  • Heat density and reliability become critical in high-performance chips.
    • +
  • Designers must trade off area, power, speed, and manufacturability.
    • +
+
+
+ +
+

Practical Concept Check

+
+

+ If a battery-powered wearable keeps toggling a large clock tree at a high + frequency, dynamic power rises quickly. A common solution is clock gating, + voltage scaling, and activity reduction so that the circuit switches only when needed. +

+
+
+
+); diff --git a/app/sem7/vlsi/content/chapter3.tsx b/app/sem7/vlsi/content/chapter3.tsx new file mode 100644 index 0000000..5346975 --- /dev/null +++ b/app/sem7/vlsi/content/chapter3.tsx @@ -0,0 +1,90 @@ +export const Ch3Content = () => ( +
+

+ Digital IC design turns logic requirements into + circuits that can be simulated, synthesized, laid out, and tested. A good designer + must think about function, timing, power, and testability at the same time. +

+ +
+ +
+

Combinational and Sequential Design

+
    +
  • Combinational logic depends only on present inputs, such as adders, encoders, and multiplexers.
    • +
  • Sequential logic depends on present input and stored state, such as counters, registers, and FSMs.
    • +
  • Clocking makes sequential circuits predictable, but also introduces setup and hold requirements.
    • +
+
+ +
+

Typical Design Flow

+
    +
  1. Write a clear specification and identify inputs, outputs, and timing needs.
    2. +
  2. Create truth tables, state diagrams, or datapath/control partitioning.
    3. +
  3. Describe the design in HDL.
    4. +
  4. Run simulation and verification using directed and corner-case tests.
    5. +
  5. Synthesize and inspect timing, area, and inferred hardware.
    6. +
  6. Improve the design for power, speed, testability, and maintainability.
    7. +
+
+ +
+

Timing Terms You Must Know

+
+
+

Setup Time

+

+ Minimum time before the active clock edge during which data must remain stable. +

+
+
+

Hold Time

+

+ Minimum time after the clock edge during which data must remain stable. +

+
+
+

Clock Skew

+

+ Difference in arrival time of the same clock at different registers. +

+
+
+

Critical Path

+

+ Longest delay path that limits the maximum safe operating frequency. +

+
+
+
+ +
+

Mini Example: 2-to-1 Multiplexer in Verilog

+ 
+        {`module mux2 (
+  input  wire a,
+  input  wire b,
+  input  wire sel,
+  output wire y
+);
+  assign y = sel ? b : a;
+endmodule`}
+
+

+ This small example shows RTL intent clearly. Synthesis tools infer the gate-level + hardware from the behavior written here. +

+
+ +
+

Verification Mindset

+
    +
  • Test normal inputs, boundary cases, and illegal transitions.
    • +
  • Check both functionality and timing assumptions.
    • +
  • Add assertions or simple self-checking logic when possible.
    • +
  • Document clock domain crossings and reset behavior early.
    • +
+
+
+); diff --git a/app/sem7/vlsi/content/chapter4.tsx b/app/sem7/vlsi/content/chapter4.tsx new file mode 100644 index 0000000..7d531ad --- /dev/null +++ b/app/sem7/vlsi/content/chapter4.tsx @@ -0,0 +1,107 @@ +export const Ch4Content = () => ( +
+

+ FPGAs, or Field Programmable Gate Arrays, are + reconfigurable chips that let designers implement digital circuits after manufacturing. + They are widely used for prototyping, custom accelerators, communication hardware, + and fast development cycles where flexibility matters. +

+ +
+ +
+

Key FPGA Building Blocks

+
    +
  • LUTs implement combinational logic.
    • +
  • Flip-flops store state and support synchronous design.
    • +
  • Block RAM stores medium-sized data on chip.
    • +
  • DSP slices speed up arithmetic such as multiply-accumulate operations.
    • +
  • Programmable routing connects logic blocks into the required circuit.
    • +
+
+ +
+

FPGA vs ASIC vs Microcontroller

+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
PlatformBest ForTrade-off
FPGAReconfigurable custom logic and rapid prototypingHigher cost and power than ASIC for volume products
ASICHigh-volume, optimized production siliconLarge upfront cost and long development cycle
MCUFirmware-driven control systemsLess parallel hardware customization
+
+
+ +
+

Basic FPGA Development Flow

+
    +
  1. Write the logic in Verilog or VHDL.
    2. +
  2. Simulate to check functionality.
    3. +
  3. Synthesize to map logic into device resources.
    4. +
  4. Place and route to assign logic and interconnects.
    5. +
  5. Generate a bitstream and program the FPGA board.
    6. +
  6. Validate using on-board LEDs, switches, displays, sensors, or communication links.
    7. +
+
+ +
+

Starter Use Cases

+
+
+

Good First Projects

+
    +
  • LED blinker with adjustable divider
    • +
  • Traffic light controller using an FSM
    • +
  • UART transmitter and receiver
    • +
  • Seven-segment display driver
    • +
+
+ +
+
+
+); diff --git a/app/sem7/vlsi/content/chapter5.tsx b/app/sem7/vlsi/content/chapter5.tsx new file mode 100644 index 0000000..4a2159e --- /dev/null +++ b/app/sem7/vlsi/content/chapter5.tsx @@ -0,0 +1,82 @@ +import Image from "next/image"; + +export const Ch5Content = () => ( +
+

+ An embedded system is a dedicated computing + system built to perform a specific task inside a larger product. Unlike general-purpose + computers, embedded systems are usually optimized for cost, power, reliability, + response time, and physical constraints. +

+ +
+ Embedded system block view with input, controller, firmware, and output +

+ Most embedded products follow the same pattern: input, processing, memory, + communication, and action. +

+
+ +
+ +
+

Main Characteristics

+
    +
  • Dedicated function rather than open-ended computing.
    • +
  • Combination of hardware and firmware in a tightly constrained environment.
    • +
  • Strong dependence on timing, interrupts, I/O interfaces, and power management.
    • +
  • Designed for repeatability, reliability, and low maintenance in the field.
    • +
+
+ +
+

Common Hardware Blocks

+
+
+

Processing

+

Microcontroller, microprocessor, DSP, or SoC

+
+
+

Memory

+

Flash, SRAM, EEPROM, cache, external storage

+
+
+

Interfaces

+

GPIO, UART, SPI, I2C, CAN, USB, Ethernet

+
+
+

Peripherals

+

Sensors, actuators, ADC, DAC, PWM, timers, watchdog

+
+
+
+ +
+

Design Constraints

+
    +
  • Power budget: especially important in portable and battery-powered products.
    • +
  • Memory size: firmware must fit into limited flash and RAM.
    • +
  • Real-world timing: delayed responses can break control behavior.
    • +
  • Environmental limits: vibration, temperature, noise, and electromagnetic interference.
    • +
+
+ +
+

Examples Around You

+
+
    +
  • Washing machine controller that reads buttons and drives motors.
    • +
  • Automotive ECU that monitors sensors and manages fuel injection.
    • +
  • Smart energy meter that samples voltage and communicates readings.
    • +
  • Medical infusion pump that must react safely and on time.
    • +
+
+
+
+); diff --git a/app/sem7/vlsi/content/chapter6.tsx b/app/sem7/vlsi/content/chapter6.tsx new file mode 100644 index 0000000..6b47b5d --- /dev/null +++ b/app/sem7/vlsi/content/chapter6.tsx @@ -0,0 +1,81 @@ +export const Ch6Content = () => ( +
+

+ Choosing the right compute engine is central to embedded design. Some products need + simple control and low power, while others need Linux, multimedia, high throughput, + or deterministic response. +

+ +
+ +
+

Microcontroller vs Microprocessor

+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
FeatureMicrocontrollerMicroprocessor
IntegrationCPU, memory, and peripherals on one chipUsually needs external memory and support chips
PowerLow power, ideal for dedicated controlHigher power, better for rich operating systems
Typical UseSensors, appliances, portable devicesSingle-board computers, gateways, multimedia systems
+
+
+ +
+

Important Peripherals

+
    +
  • GPIO: digital pins for LEDs, switches, relays, and simple status signals.
    • +
  • Timers and counters: used for delays, PWM, periodic sampling, and capture events.
    • +
  • ADC and DAC: bridge analog sensors and digital processing.
    • +
  • UART, SPI, and I2C: essential protocols for communication with displays, sensors, and modules.
    • +
  • Interrupt controller: lets urgent events preempt the normal program flow.
    • +
+
+ +
+

Processor Families You Will Commonly Meet

+
+
+

Cortex-M Class

+

+ Great for bare-metal or RTOS-based control applications with low power needs. +

+
+
+

Cortex-A Class

+

+ Stronger processors that can run Linux, UI stacks, and richer applications. +

+
+
+
+ +
+

Selection Checklist

+
+ Choose the device by asking: How fast must it respond? How much memory is needed? + Is an RTOS or Linux required? Which interfaces are mandatory? What is the power + budget and production cost target? +
+
+
+); diff --git a/app/sem7/vlsi/content/chapter7.tsx b/app/sem7/vlsi/content/chapter7.tsx new file mode 100644 index 0000000..1cf077c --- /dev/null +++ b/app/sem7/vlsi/content/chapter7.tsx @@ -0,0 +1,119 @@ +export const Ch7Content = () => ( +
+

+ Arduino and Raspberry Pi are popular teaching and prototyping platforms, but they + serve different purposes. Arduino is centered around a microcontroller and direct + hardware control. Raspberry Pi is a compact computer that can run Linux and support + networking, storage, and higher-level applications. +

+ +
+ +
+

Quick Comparison

+
+ + + + + + + + + + + + + + + + + + + + +
PlatformStrengthBest Fit
ArduinoSimple hardware control and deterministic loopsSensors, actuators, robotics basics, control tasks
Raspberry PiLinux environment, networking, camera, storageIoT gateways, edge apps, Python projects, dashboards
+
+
+ +
+

Starter Arduino Workflow

+
    +
  1. Install the Arduino IDE and select the correct board.
    2. +
  2. Connect a simple circuit such as an LED with a resistor.
    3. +
  3. Write a short sketch, compile it, and upload it.
    4. +
  4. Use Serial Monitor for debugging and sensor output.
    5. +
+ 
+        {`void setup() {
+  pinMode(13, OUTPUT);
+}
+
+void loop() {
+  digitalWrite(13, HIGH);
+  delay(500);
+  digitalWrite(13, LOW);
+  delay(500);
+}`}
+
+
+ +
+

Starter Raspberry Pi Workflow

+
    +
  • Flash Raspberry Pi OS to a microSD card and complete initial setup.
    • +
  • Use Python or shell tools to access GPIO, files, and network services.
    • +
  • Connect sensors through GPIO, I2C, SPI, or USB peripherals.
    • +
  • Prototype dashboards, logging pipelines, or lightweight web services.
    • +
+
+ +
+

Safety and Good Practice

+
+
    +
  • Check operating voltage before wiring sensors or modules.
    • +
  • Do not drive motors directly from logic pins without driver circuitry.
    • +
  • Label pin mappings and power rails before powering the board.
    • +
  • Use serial logs, LEDs, and simple test cases while debugging.
    • +
+
+
+ +
+

Official Learning Resources

+ +
+
+); diff --git a/app/sem7/vlsi/content/chapter8.tsx b/app/sem7/vlsi/content/chapter8.tsx new file mode 100644 index 0000000..30b2e31 --- /dev/null +++ b/app/sem7/vlsi/content/chapter8.tsx @@ -0,0 +1,89 @@ +export const Ch8Content = () => ( +
+

+ A real-time system is judged not only by correct + results, but also by whether those results are produced within the required time. + This is why scheduling, latency, jitter, and predictable execution are central in + embedded applications. +

+ +
+ +
+

Types of Real-time Systems

+
+
+

Hard Real-time

+

Missing a deadline can cause failure or danger.

+
+
+

Firm Real-time

+

Late results lose value, but occasional misses may be tolerable.

+
+
+

Soft Real-time

+

Performance degrades when late, but the system still continues.

+
+
+
+ +
+

Important Terms

+
    +
  • Deadline: latest acceptable completion time for a task.
    • +
  • Latency: delay between an event and the system response.
    • +
  • Jitter: variation in response time across repeated executions.
    • +
  • Priority inversion: a high-priority task is blocked by lower-priority work.
    • +
+
+ +
+

Scheduling Approaches

+
+ + + + + + + + + + + + + + + + + + + + +
MethodIdeaGood For
Rate MonotonicShorter period tasks get higher priorityPeriodic control tasks
Earliest Deadline FirstTask with the closest deadline runs firstDynamic scheduling with variable timing
+
+
+ +
+

Practical Example

+
+

+ Consider an industrial temperature controller that samples a sensor every + 10 ms, updates a control signal, and logs data every 500 ms. The control + task must meet its deadline consistently, while logging can be delayed slightly + without endangering the process. +

+
+
+ +
+

Engineering Tips

+
    +
  • Keep interrupt service routines short and deterministic.
    • +
  • Use buffers and queues to separate time-critical code from background tasks.
    • +
  • Measure worst-case execution time rather than average time only.
    • +
  • Add watchdog timers and fault handling for safety-oriented systems.
    • +
+
+
+); diff --git a/app/sem7/vlsi/content/chapter9.tsx b/app/sem7/vlsi/content/chapter9.tsx new file mode 100644 index 0000000..9ebe40d --- /dev/null +++ b/app/sem7/vlsi/content/chapter9.tsx @@ -0,0 +1,117 @@ +export const Ch9Content = () => ( +
+

+ The best way to become comfortable with this subject is to connect theory with + small buildable projects. This final section collects project ideas, books, and + external resources you can use after finishing the chapter notes. +

+ +
+ +
+

Mini Project Ideas

+
+
+

FPGA Traffic Light Controller

+

+ Practice finite state machines, clock division, and hardware testing. +

+
+
+

Arduino Smart Irrigation Node

+

+ Read soil moisture, drive a relay, and log threshold-based decisions. +

+
+
+

Raspberry Pi Edge Dashboard

+

+ Collect sensor data, visualize it, and trigger alerts over the network. +

+
+
+

RTOS Periodic Task Demo

+

+ Compare task periods, deadlines, and CPU utilization using timers and logs. +

+
+
+
+ +
+

Reference Books

+
    +
  • CMOS VLSI Design by Weste and Harris
    • +
  • Digital Integrated Circuits by Rabaey, Chandrakasan, and Nikolic
    • +
  • Embedded Systems by Raj Kamal
    • +
  • The 8051 Microcontroller and Embedded Systems by Mazidi
    • +
  • Real-Time Systems by Jane Liu
    • +
+
+ +
+

Official and High-value Resource Links

+ +
+ +
+

How to Revise for Exams and Interviews

+
+ Focus on the design flow, transistor-level intuition, timing terms, embedded I/O + protocols, and one practical example per chapter. If you can explain one mini + project clearly, your understanding becomes far stronger than memorizing theory alone. +
+
+
+); diff --git a/app/sem7/vlsi/layout.tsx b/app/sem7/vlsi/layout.tsx new file mode 100644 index 0000000..b80a5f6 --- /dev/null +++ b/app/sem7/vlsi/layout.tsx @@ -0,0 +1,23 @@ +import Navbar from "../../components/navbar"; +import Sidebar from "./components/sidebar"; + +export const metadata = { + title: "VLSI and Embedded Systems | openCSE", + description: "Free and open notes for VLSI and Embedded Systems", +}; + +export default function VLSILayout({ children }: { children: React.ReactNode }) { + return ( +
+ + +
+ + +
+
{children}
+
+
+
+ ); +} diff --git a/app/sem7/vlsi/page.tsx b/app/sem7/vlsi/page.tsx new file mode 100644 index 0000000..bd75d3f --- /dev/null +++ b/app/sem7/vlsi/page.tsx @@ -0,0 +1,5 @@ +import { redirect } from "next/navigation"; + +export default function Page() { + redirect("/sem7/vlsi/ch0"); +} diff --git a/public/sem7/vlsi/embedded-system-stack.svg b/public/sem7/vlsi/embedded-system-stack.svg new file mode 100644 index 0000000..77bc228 --- /dev/null +++ b/public/sem7/vlsi/embedded-system-stack.svg @@ -0,0 +1,41 @@ + + + Embedded System View + Input, processing, memory, communication, and output in one dedicated product + + + Sensors / + Input + + + Controller + MCU / MPU / SoC + Interrupts, timers, buses, logic + + + Memory + Flash, RAM, EEPROM + + + Actuators / Output + Motor, display, relay, alarm + + + Firmware + Communication + Power Management + + + + + + + + + + + + + + + + + diff --git a/public/sem7/vlsi/vlsi-design-flow.svg b/public/sem7/vlsi/vlsi-design-flow.svg new file mode 100644 index 0000000..6e634bd --- /dev/null +++ b/public/sem7/vlsi/vlsi-design-flow.svg @@ -0,0 +1,48 @@ + + + VLSI Design Flow + From product idea to manufacturable silicon + + + + Specification + + + RTL + + + Verification + + + Synthesis + + + Layout + + + Test + + + + + + + + + + + + + + + + + + + Goal definition + Behavior description + Simulation and bug fixing + Gate mapping + Place and route + Sign-off +