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bjorn-helgaasgregkh
bjorn-helgaas
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gregkh
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PCI: Probe bridge window attributes once at enumeration-time
commit 51c48b3 upstream. pci_bridge_check_ranges() determines whether a bridge supports the optional I/O and prefetchable memory windows and sets the flag bits in the bridge resources. This *could* be done once during enumeration except that the resource allocation code completely clears the flag bits, e.g., in the pci_assign_unassigned_bridge_resources() path. The problem with pci_bridge_check_ranges() in the resource allocation path is that we may allocate resources after devices have been claimed by drivers, and pci_bridge_check_ranges() *changes* the window registers to determine whether they're writable. This may break concurrent accesses to devices behind the bridge. Add a new pci_read_bridge_windows() to determine whether a bridge supports the optional windows, call it once during enumeration, remember the results, and change pci_bridge_check_ranges() so it doesn't touch the bridge windows but sets the flag bits based on those remembered results. Link: https://lore.kernel.org/linux-pci/1506151482-113560-1-git-send-email-wangzhou1@hisilicon.com Link: https://lists.gnu.org/archive/html/qemu-devel/2018-12/msg02082.html Reported-by: Yandong Xu <xuyandong2@huawei.com> Tested-by: Yandong Xu <xuyandong2@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Sagi Grimberg <sagi@grimberg.me> Cc: Ofer Hayut <ofer@lightbitslabs.com> Cc: Roy Shterman <roys@lightbitslabs.com> Cc: Keith Busch <keith.busch@intel.com> Cc: Zhou Wang <wangzhou1@hisilicon.com> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=208371 Signed-off-by: Dima Stepanov <dimastep@yandex-team.ru> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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3 files changed

Lines changed: 59 additions & 41 deletions

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‎drivers/pci/probe.c‎

Lines changed: 52 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -348,6 +348,57 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
348348
}
349349
}
350350

351+
static void pci_read_bridge_windows(struct pci_dev *bridge)
352+
{
353+
u16 io;
354+
u32 pmem, tmp;
355+
356+
pci_read_config_word(bridge, PCI_IO_BASE, &io);
357+
if (!io) {
358+
pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
359+
pci_read_config_word(bridge, PCI_IO_BASE, &io);
360+
pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
361+
}
362+
if (io)
363+
bridge->io_window = 1;
364+
365+
/*
366+
* DECchip 21050 pass 2 errata: the bridge may miss an address
367+
* disconnect boundary by one PCI data phase. Workaround: do not
368+
* use prefetching on this device.
369+
*/
370+
if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
371+
return;
372+
373+
pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
374+
if (!pmem) {
375+
pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
376+
0xffe0fff0);
377+
pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
378+
pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
379+
}
380+
if (!pmem)
381+
return;
382+
383+
bridge->pref_window = 1;
384+
385+
if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
386+
387+
/*
388+
* Bridge claims to have a 64-bit prefetchable memory
389+
* window; verify that the upper bits are actually
390+
* writable.
391+
*/
392+
pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem);
393+
pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
394+
0xffffffff);
395+
pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
396+
pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem);
397+
if (tmp)
398+
bridge->pref_64_window = 1;
399+
}
400+
}
401+
351402
static void pci_read_bridge_io(struct pci_bus *child)
352403
{
353404
struct pci_dev *dev = child->self;
@@ -1712,6 +1763,7 @@ int pci_setup_device(struct pci_dev *dev)
17121763
pci_read_irq(dev);
17131764
dev->transparent = ((dev->class & 0xff) == 1);
17141765
pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1766+
pci_read_bridge_windows(dev);
17151767
set_pcie_hotplug_bridge(dev);
17161768
pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
17171769
if (pos) {

‎drivers/pci/setup-bus.c‎

Lines changed: 4 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -735,58 +735,21 @@ int pci_claim_bridge_resource(struct pci_dev *bridge, int i)
735735
base/limit registers must be read-only and read as 0. */
736736
static void pci_bridge_check_ranges(struct pci_bus *bus)
737737
{
738-
u16 io;
739-
u32 pmem;
740738
struct pci_dev *bridge = bus->self;
741-
struct resource *b_res;
739+
struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
742740

743-
b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
744741
b_res[1].flags |= IORESOURCE_MEM;
745742

746-
pci_read_config_word(bridge, PCI_IO_BASE, &io);
747-
if (!io) {
748-
pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
749-
pci_read_config_word(bridge, PCI_IO_BASE, &io);
750-
pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
751-
}
752-
if (io)
743+
if (bridge->io_window)
753744
b_res[0].flags |= IORESOURCE_IO;
754745

755-
/* DECchip 21050 pass 2 errata: the bridge may miss an address
756-
disconnect boundary by one PCI data phase.
757-
Workaround: do not use prefetching on this device. */
758-
if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
759-
return;
760-
761-
pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
762-
if (!pmem) {
763-
pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
764-
0xffe0fff0);
765-
pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
766-
pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
767-
}
768-
if (pmem) {
746+
if (bridge->pref_window) {
769747
b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
770-
if ((pmem & PCI_PREF_RANGE_TYPE_MASK) ==
771-
PCI_PREF_RANGE_TYPE_64) {
748+
if (bridge->pref_64_window) {
772749
b_res[2].flags |= IORESOURCE_MEM_64;
773750
b_res[2].flags |= PCI_PREF_RANGE_TYPE_64;
774751
}
775752
}
776-
777-
/* double check if bridge does support 64 bit pref */
778-
if (b_res[2].flags & IORESOURCE_MEM_64) {
779-
u32 mem_base_hi, tmp;
780-
pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32,
781-
&mem_base_hi);
782-
pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
783-
0xffffffff);
784-
pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
785-
if (!tmp)
786-
b_res[2].flags &= ~IORESOURCE_MEM_64;
787-
pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
788-
mem_base_hi);
789-
}
790753
}
791754

792755
/* Helper function for sizing routines: find first available

‎include/linux/pci.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -373,6 +373,9 @@ struct pci_dev {
373373
bool match_driver; /* Skip attaching driver */
374374

375375
unsigned int transparent:1; /* Subtractive decode bridge */
376+
unsigned int io_window:1; /* Bridge has I/O window */
377+
unsigned int pref_window:1; /* Bridge has pref mem window */
378+
unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
376379
unsigned int multifunction:1; /* Multi-function device */
377380

378381
unsigned int is_busmaster:1; /* Is busmaster */

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