Merge branch 'linux-5.15-trunk/at91/pm' into linux-5.15-mchp

Author: cristibirsan

arch/arm/mach-at91/pm_suspend.S

@@ -193,27 +193,16 @@ sr_ena_2:
 	/* Put DDR PHY's DLL in bypass mode for non-backup modes. */
 	cmp	r7, #AT91_PM_BACKUP
 	beq	sr_ena_3
-	ldr	tmp1, [r3, #DDR3PHY_PIR]
-	orr	tmp1, tmp1, #DDR3PHY_PIR_DLLBYP
-	str	tmp1, [r3, #DDR3PHY_PIR]
+
+	ldr	tmp1, [r3, #DDR3PHY_DX0DLLCR]
+	orr	tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS
+	str	tmp1, [r3, #DDR3PHY_DX0DLLCR]
+
+	ldr	tmp1, [r3, #DDR3PHY_DX1DLLCR]
+	orr	tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS
+	str	tmp1, [r3, #DDR3PHY_DX1DLLCR]
 
 sr_ena_3:
-	/* Power down DDR PHY data receivers. */
-	ldr	tmp1, [r3, #DDR3PHY_DXCCR]
-	orr	tmp1, tmp1, #DDR3PHY_DXCCR_DXPDR
-	str	tmp1, [r3, #DDR3PHY_DXCCR]
-
-	/* Power down ADDR/CMD IO. */
-	ldr	tmp1, [r3, #DDR3PHY_ACIOCR]
-	orr	tmp1, tmp1, #DDR3PHY_ACIORC_ACPDD
-	orr	tmp1, tmp1, #DDR3PHY_ACIOCR_CKPDD_CK0
-	orr	tmp1, tmp1, #DDR3PHY_ACIOCR_CSPDD_CS0
-	str	tmp1, [r3, #DDR3PHY_ACIOCR]
-
-	/* Power down ODT. */
-	ldr	tmp1, [r3, #DDR3PHY_DSGCR]
-	orr	tmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0
-	str	tmp1, [r3, #DDR3PHY_DSGCR]
 .endm
 
 /**
@@ -225,27 +214,13 @@ sr_ena_3:
 	ldr	r2, .sramc_base
 	ldr	r3, .sramc_phy_base
 
-	/* Power up DDR PHY data receivers. */
-	ldr	tmp1, [r3, #DDR3PHY_DXCCR]
-	bic	tmp1, tmp1, #DDR3PHY_DXCCR_DXPDR
-	str	tmp1, [r3, #DDR3PHY_DXCCR]
-
-	/* Power up the output of CK and CS pins. */
-	ldr	tmp1, [r3, #DDR3PHY_ACIOCR]
-	bic	tmp1, tmp1, #DDR3PHY_ACIORC_ACPDD
-	bic	tmp1, tmp1, #DDR3PHY_ACIOCR_CKPDD_CK0
-	bic	tmp1, tmp1, #DDR3PHY_ACIOCR_CSPDD_CS0
-	str	tmp1, [r3, #DDR3PHY_ACIOCR]
-
-	/* Power up ODT. */
-	ldr	tmp1, [r3, #DDR3PHY_DSGCR]
-	bic	tmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0
-	str	tmp1, [r3, #DDR3PHY_DSGCR]
-
-	/* Take DDR PHY's DLL out of bypass mode. */
-	ldr	tmp1, [r3, #DDR3PHY_PIR]
-	bic	tmp1, tmp1, #DDR3PHY_PIR_DLLBYP
-	str	tmp1, [r3, #DDR3PHY_PIR]
+	ldr	tmp1, [r3, #DDR3PHY_DX0DLLCR]
+	bic	tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS
+	str	tmp1, [r3, #DDR3PHY_DX0DLLCR]
+
+	ldr	tmp1, [r3, #DDR3PHY_DX1DLLCR]
+	bic	tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS
+	str	tmp1, [r3, #DDR3PHY_DX1DLLCR]
 
 	/* Enable quasi-dynamic programming. */
 	mov	tmp1, #0

include/soc/at91/sama7-ddr.h

@@ -39,6 +39,10 @@
 
 #define DDR3PHY_ZQ0SR0				(0x188)		/* ZQ status register 0 */
 
+#define	DDR3PHY_DX0DLLCR			(0x1CC)		/* DDR3PHY DATX8 DLL Control Register */
+#define	DDR3PHY_DX1DLLCR			(0x20C)		/* DDR3PHY DATX8 DLL Control Register */
+#define		DDR3PHY_DXDLLCR_DLLDIS		(1 << 31)	/* DLL Disable */
+
 /* UDDRC */
 #define UDDRC_STAT				(0x04)		/* UDDRC Operating Mode Status Register */
 #define		UDDRC_STAT_SELFREF_TYPE_DIS	(0x0 << 4)	/* SDRAM is not in Self-refresh */