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Merge tag 'drm-intel-fixes-2017-10-26' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes
One fix for stable: - fix perf enable/disable ioctls for 32bits (Lionel) Plus GVT fixes: - Fix per_ctx_bb check (Zhenyu) - Fix GPU hang of Linux guest (Xion) - Refine MMIO_RING_F to check for presence of VCS2 ring (Zhi) * tag 'drm-intel-fixes-2017-10-26' of git://anongit.freedesktop.org/drm/drm-intel: drm/i915/gvt: Adding ACTHD mmio read handler drm/i915/gvt: Extract mmio_read_from_hw() common function drm/i915/gvt: Refine MMIO_RING_F() drm/i915/gvt: properly check per_ctx bb valid state
2 parents 522dbb3 + 894e287 commit ce485df

5 files changed

Lines changed: 15 additions & 65 deletions

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‎drivers/gpu/drm/i915/gvt/cmd_parser.c‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2723,6 +2723,9 @@ static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
27232723
uint32_t per_ctx_start[CACHELINE_DWORDS] = {0};
27242724
unsigned char *bb_start_sva;
27252725

2726+
if (!wa_ctx->per_ctx.valid)
2727+
return 0;
2728+
27262729
per_ctx_start[0] = 0x18800001;
27272730
per_ctx_start[1] = wa_ctx->per_ctx.guest_gma;
27282731

‎drivers/gpu/drm/i915/gvt/execlist.c‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -701,8 +701,7 @@ static int submit_context(struct intel_vgpu *vgpu, int ring_id,
701701
CACHELINE_BYTES;
702702
workload->wa_ctx.per_ctx.guest_gma =
703703
per_ctx & PER_CTX_ADDR_MASK;
704-
705-
WARN_ON(workload->wa_ctx.indirect_ctx.size && !(per_ctx & 0x1));
704+
workload->wa_ctx.per_ctx.valid = per_ctx & 1;
706705
}
707706

708707
if (emulate_schedule_in)

‎drivers/gpu/drm/i915/gvt/handlers.c‎

Lines changed: 10 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -1429,18 +1429,7 @@ static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset,
14291429
return 0;
14301430
}
14311431

1432-
static int ring_timestamp_mmio_read(struct intel_vgpu *vgpu,
1433-
unsigned int offset, void *p_data, unsigned int bytes)
1434-
{
1435-
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1436-
1437-
mmio_hw_access_pre(dev_priv);
1438-
vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset));
1439-
mmio_hw_access_post(dev_priv);
1440-
return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1441-
}
1442-
1443-
static int instdone_mmio_read(struct intel_vgpu *vgpu,
1432+
static int mmio_read_from_hw(struct intel_vgpu *vgpu,
14441433
unsigned int offset, void *p_data, unsigned int bytes)
14451434
{
14461435
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
@@ -1589,6 +1578,8 @@ static int ring_reset_ctl_write(struct intel_vgpu *vgpu,
15891578
MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
15901579
MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
15911580
MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
1581+
if (HAS_BSD2(dev_priv)) \
1582+
MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
15921583
} while (0)
15931584

15941585
#define MMIO_RING_D(prefix, d) \
@@ -1635,10 +1626,9 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
16351626
#undef RING_REG
16361627

16371628
#define RING_REG(base) (base + 0x6c)
1638-
MMIO_RING_DFH(RING_REG, D_ALL, 0, instdone_mmio_read, NULL);
1639-
MMIO_DH(RING_REG(GEN8_BSD2_RING_BASE), D_ALL, instdone_mmio_read, NULL);
1629+
MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
16401630
#undef RING_REG
1641-
MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, instdone_mmio_read, NULL);
1631+
MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
16421632

16431633
MMIO_GM_RDR(0x2148, D_ALL, NULL, NULL);
16441634
MMIO_GM_RDR(CCID, D_ALL, NULL, NULL);
@@ -1648,7 +1638,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
16481638
MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL);
16491639
MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL);
16501640
MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
1651-
MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, NULL, NULL);
1641+
MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, mmio_read_from_hw, NULL);
16521642
MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL);
16531643

16541644
/* RING MODE */
@@ -1662,9 +1652,9 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
16621652
MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
16631653
NULL, NULL);
16641654
MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
1665-
ring_timestamp_mmio_read, NULL);
1655+
mmio_read_from_hw, NULL);
16661656
MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
1667-
ring_timestamp_mmio_read, NULL);
1657+
mmio_read_from_hw, NULL);
16681658

16691659
MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
16701660
MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
@@ -2411,9 +2401,6 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
24112401
struct drm_i915_private *dev_priv = gvt->dev_priv;
24122402
int ret;
24132403

2414-
MMIO_DFH(RING_IMR(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS, NULL,
2415-
intel_vgpu_reg_imr_handler);
2416-
24172404
MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
24182405
MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
24192406
MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
@@ -2476,68 +2463,34 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
24762463
MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
24772464
intel_vgpu_reg_master_irq_handler);
24782465

2479-
MMIO_DFH(RING_HWSTAM(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2480-
F_CMD_ACCESS, NULL, NULL);
2481-
MMIO_DFH(0x1c134, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2482-
2483-
MMIO_DFH(RING_TAIL(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS,
2484-
NULL, NULL);
2485-
MMIO_DFH(RING_HEAD(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2486-
F_CMD_ACCESS, NULL, NULL);
2487-
MMIO_GM_RDR(RING_START(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL);
2488-
MMIO_DFH(RING_CTL(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS,
2489-
NULL, NULL);
2490-
MMIO_DFH(RING_ACTHD(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2491-
F_CMD_ACCESS, NULL, NULL);
2492-
MMIO_DFH(RING_ACTHD_UDW(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2493-
F_CMD_ACCESS, NULL, NULL);
2494-
MMIO_DFH(0x1c29c, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL,
2495-
ring_mode_mmio_write);
2496-
MMIO_DFH(RING_MI_MODE(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2497-
F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2498-
MMIO_DFH(RING_INSTPM(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2499-
F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2500-
MMIO_DFH(RING_TIMESTAMP(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS,
2501-
ring_timestamp_mmio_read, NULL);
2502-
2503-
MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2466+
MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS,
2467+
mmio_read_from_hw, NULL);
25042468

25052469
#define RING_REG(base) (base + 0xd0)
25062470
MMIO_RING_F(RING_REG, 4, F_RO, 0,
25072471
~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
25082472
ring_reset_ctl_write);
2509-
MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO, 0,
2510-
~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
2511-
ring_reset_ctl_write);
25122473
#undef RING_REG
25132474

25142475
#define RING_REG(base) (base + 0x230)
25152476
MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
2516-
MMIO_DH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, elsp_mmio_write);
25172477
#undef RING_REG
25182478

25192479
#define RING_REG(base) (base + 0x234)
25202480
MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS,
25212481
NULL, NULL);
2522-
MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO | F_CMD_ACCESS, 0,
2523-
~0LL, D_BDW_PLUS, NULL, NULL);
25242482
#undef RING_REG
25252483

25262484
#define RING_REG(base) (base + 0x244)
25272485
MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2528-
MMIO_DFH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS,
2529-
NULL, NULL);
25302486
#undef RING_REG
25312487

25322488
#define RING_REG(base) (base + 0x370)
25332489
MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
2534-
MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 48, F_RO, 0, ~0, D_BDW_PLUS,
2535-
NULL, NULL);
25362490
#undef RING_REG
25372491

25382492
#define RING_REG(base) (base + 0x3a0)
25392493
MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
2540-
MMIO_DFH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
25412494
#undef RING_REG
25422495

25432496
MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
@@ -2557,11 +2510,9 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
25572510

25582511
#define RING_REG(base) (base + 0x270)
25592512
MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL);
2560-
MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL);
25612513
#undef RING_REG
25622514

25632515
MMIO_RING_GM_RDR(RING_HWS_PGA, D_BDW_PLUS, NULL, NULL);
2564-
MMIO_GM_RDR(RING_HWS_PGA(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL);
25652516

25662517
MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
25672518

@@ -2849,7 +2800,6 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
28492800
MMIO_D(0x65f08, D_SKL | D_KBL);
28502801
MMIO_D(0x320f0, D_SKL | D_KBL);
28512802

2852-
MMIO_DFH(_REG_VCS2_EXCC, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
28532803
MMIO_D(0x70034, D_SKL_PLUS);
28542804
MMIO_D(0x71034, D_SKL_PLUS);
28552805
MMIO_D(0x72034, D_SKL_PLUS);

‎drivers/gpu/drm/i915/gvt/reg.h‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -54,9 +54,6 @@
5454

5555
#define VGT_SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _PLANE_STRIDE_2_B)
5656

57-
#define _REG_VECS_EXCC 0x1A028
58-
#define _REG_VCS2_EXCC 0x1c028
59-
6057
#define _REG_701C0(pipe, plane) (0x701c0 + pipe * 0x1000 + (plane - 1) * 0x100)
6158
#define _REG_701C4(pipe, plane) (0x701c4 + pipe * 0x1000 + (plane - 1) * 0x100)
6259

‎drivers/gpu/drm/i915/gvt/scheduler.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -68,6 +68,7 @@ struct shadow_indirect_ctx {
6868
struct shadow_per_ctx {
6969
unsigned long guest_gma;
7070
unsigned long shadow_gma;
71+
unsigned valid;
7172
};
7273

7374
struct intel_shadow_wa_ctx {

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