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alexdeuchergregkh
alexdeucher
authored and
gregkh
committed
drm/amdgpu: add support for IP discovery gc_info table v2
commit 5e713c6 upstream. Used on gfx9 based systems. Fixes incorrect CU counts reported in the kernel log. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1833 Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
1 parent 28863ff commit b855333

2 files changed

Lines changed: 103 additions & 22 deletions

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‎drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c‎

Lines changed: 54 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -372,38 +372,70 @@ int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id,
372372
return -EINVAL;
373373
}
374374

375+
union gc_info {
376+
struct gc_info_v1_0 v1;
377+
struct gc_info_v2_0 v2;
378+
};
379+
375380
int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
376381
{
377382
struct binary_header *bhdr;
378-
struct gc_info_v1_0 *gc_info;
383+
union gc_info *gc_info;
379384

380385
if (!adev->mman.discovery_bin) {
381386
DRM_ERROR("ip discovery uninitialized\n");
382387
return -EINVAL;
383388
}
384389

385390
bhdr = (struct binary_header *)adev->mman.discovery_bin;
386-
gc_info = (struct gc_info_v1_0 *)(adev->mman.discovery_bin +
391+
gc_info = (union gc_info *)(adev->mman.discovery_bin +
387392
le16_to_cpu(bhdr->table_list[GC].offset));
388-
389-
adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->gc_num_se);
390-
adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->gc_num_wgp0_per_sa) +
391-
le32_to_cpu(gc_info->gc_num_wgp1_per_sa));
392-
adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->gc_num_sa_per_se);
393-
adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->gc_num_rb_per_se);
394-
adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->gc_num_gl2c);
395-
adev->gfx.config.max_gprs = le32_to_cpu(gc_info->gc_num_gprs);
396-
adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->gc_num_max_gs_thds);
397-
adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->gc_gs_table_depth);
398-
adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->gc_gsprim_buff_depth);
399-
adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->gc_double_offchip_lds_buffer);
400-
adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->gc_wave_size);
401-
adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->gc_max_waves_per_simd);
402-
adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->gc_max_scratch_slots_per_cu);
403-
adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->gc_lds_size);
404-
adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->gc_num_sc_per_se) /
405-
le32_to_cpu(gc_info->gc_num_sa_per_se);
406-
adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->gc_num_packer_per_sc);
407-
393+
switch (gc_info->v1.header.version_major) {
394+
case 1:
395+
adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se);
396+
adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) +
397+
le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa));
398+
adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
399+
adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se);
400+
adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c);
401+
adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs);
402+
adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds);
403+
adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth);
404+
adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth);
405+
adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer);
406+
adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size);
407+
adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd);
408+
adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu);
409+
adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size);
410+
adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) /
411+
le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
412+
adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc);
413+
break;
414+
case 2:
415+
adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se);
416+
adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh);
417+
adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
418+
adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se);
419+
adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs);
420+
adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs);
421+
adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds);
422+
adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth);
423+
adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth);
424+
adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer);
425+
adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size);
426+
adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd);
427+
adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu);
428+
adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size);
429+
adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) /
430+
le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
431+
adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc);
432+
break;
433+
default:
434+
dev_err(adev->dev,
435+
"Unhandled GC info table %d.%d\n",
436+
gc_info->v1.header.version_major,
437+
gc_info->v1.header.version_minor);
438+
return -EINVAL;
439+
}
408440
return 0;
409441
}

‎drivers/gpu/drm/amd/include/discovery.h‎

Lines changed: 49 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -143,6 +143,55 @@ struct gc_info_v1_0 {
143143
uint32_t gc_num_gl2a;
144144
};
145145

146+
struct gc_info_v1_1 {
147+
struct gpu_info_header header;
148+
149+
uint32_t gc_num_se;
150+
uint32_t gc_num_wgp0_per_sa;
151+
uint32_t gc_num_wgp1_per_sa;
152+
uint32_t gc_num_rb_per_se;
153+
uint32_t gc_num_gl2c;
154+
uint32_t gc_num_gprs;
155+
uint32_t gc_num_max_gs_thds;
156+
uint32_t gc_gs_table_depth;
157+
uint32_t gc_gsprim_buff_depth;
158+
uint32_t gc_parameter_cache_depth;
159+
uint32_t gc_double_offchip_lds_buffer;
160+
uint32_t gc_wave_size;
161+
uint32_t gc_max_waves_per_simd;
162+
uint32_t gc_max_scratch_slots_per_cu;
163+
uint32_t gc_lds_size;
164+
uint32_t gc_num_sc_per_se;
165+
uint32_t gc_num_sa_per_se;
166+
uint32_t gc_num_packer_per_sc;
167+
uint32_t gc_num_gl2a;
168+
uint32_t gc_num_tcp_per_sa;
169+
uint32_t gc_num_sdp_interface;
170+
uint32_t gc_num_tcps;
171+
};
172+
173+
struct gc_info_v2_0 {
174+
struct gpu_info_header header;
175+
176+
uint32_t gc_num_se;
177+
uint32_t gc_num_cu_per_sh;
178+
uint32_t gc_num_sh_per_se;
179+
uint32_t gc_num_rb_per_se;
180+
uint32_t gc_num_tccs;
181+
uint32_t gc_num_gprs;
182+
uint32_t gc_num_max_gs_thds;
183+
uint32_t gc_gs_table_depth;
184+
uint32_t gc_gsprim_buff_depth;
185+
uint32_t gc_parameter_cache_depth;
186+
uint32_t gc_double_offchip_lds_buffer;
187+
uint32_t gc_wave_size;
188+
uint32_t gc_max_waves_per_simd;
189+
uint32_t gc_max_scratch_slots_per_cu;
190+
uint32_t gc_lds_size;
191+
uint32_t gc_num_sc_per_se;
192+
uint32_t gc_num_packer_per_sc;
193+
};
194+
146195
typedef struct harvest_info_header {
147196
uint32_t signature; /* Table Signature */
148197
uint32_t version; /* Table Version */

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