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| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | +%YAML 1.2 |
| 3 | +--- |
| 4 | +$id: http://devicetree.org/schemas/media/snps,dw-csi.yaml# |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | + |
| 7 | +title: Synopsys DesignWare CSI-2 Host controller (csi2host) |
| 8 | + |
| 9 | +maintainers: |
| 10 | + - Eugen Hristev <eugen.hristev@microchip.com> |
| 11 | + |
| 12 | +description: |
| 13 | + CSI2HOST is used to receive image coming from an MIPI CSI-2 compatible |
| 14 | + camera. It will convert the incoming CSI-2 stream into a dedicated |
| 15 | + interface called the Synopsys IDI (Image Data Interface). |
| 16 | + This interface is a 32-bit SoC internal only, and can be assimilated |
| 17 | + with a CSI-2 interface. |
| 18 | + |
| 19 | +properties: |
| 20 | + compatible: |
| 21 | + const: snps,dw-csi |
| 22 | + |
| 23 | + reg: |
| 24 | + maxItems: 1 |
| 25 | + |
| 26 | + clocks: |
| 27 | + maxItems: 2 |
| 28 | + |
| 29 | + clock-names: |
| 30 | + description: |
| 31 | + CSI2HOST can have two clocks connected. One clock is the |
| 32 | + peripheral clock for the inside functionality of the hardware block. |
| 33 | + This is named 'perclk'. The second clock can be the phy clock, |
| 34 | + which is used to clock the phy via an internal link. |
| 35 | + This clock is named 'phyclk', phy clock. |
| 36 | + items: |
| 37 | + - const: perclk |
| 38 | + - const: phyclk |
| 39 | + |
| 40 | + phys: |
| 41 | + maxItems: 1 |
| 42 | + description: MIPI D-PHY |
| 43 | + |
| 44 | + phy-names: |
| 45 | + items: |
| 46 | + - const: dphy |
| 47 | + |
| 48 | + resets: |
| 49 | + maxItems: 1 |
| 50 | + |
| 51 | + interrupts: |
| 52 | + maxItems: 1 |
| 53 | + |
| 54 | + ports: |
| 55 | + $ref: /schemas/graph.yaml#/properties/ports |
| 56 | + |
| 57 | + properties: |
| 58 | + port@0: |
| 59 | + $ref: /schemas/graph.yaml#/$defs/port-base |
| 60 | + unevaluatedProperties: false |
| 61 | + description: |
| 62 | + Input port node, single endpoint describing the input port. |
| 63 | + |
| 64 | + properties: |
| 65 | + endpoint: |
| 66 | + $ref: video-interfaces.yaml# |
| 67 | + unevaluatedProperties: false |
| 68 | + description: Endpoint connected to input device |
| 69 | + |
| 70 | + properties: |
| 71 | + bus-type: |
| 72 | + const: 4 |
| 73 | + |
| 74 | + data-lanes: |
| 75 | + minItems: 1 |
| 76 | + maxItems: 4 |
| 77 | + items: |
| 78 | + maximum: 4 |
| 79 | + |
| 80 | + clock-lanes: |
| 81 | + maxItems: 1 |
| 82 | + |
| 83 | + remote-endpoint: true |
| 84 | + |
| 85 | + port@1: |
| 86 | + $ref: /schemas/graph.yaml#/$defs/port-base |
| 87 | + unevaluatedProperties: false |
| 88 | + description: |
| 89 | + Output port node, single endpoint describing the output port. |
| 90 | + |
| 91 | + properties: |
| 92 | + endpoint: |
| 93 | + unevaluatedProperties: false |
| 94 | + $ref: video-interfaces.yaml# |
| 95 | + description: Endpoint connected to output device |
| 96 | + |
| 97 | + properties: |
| 98 | + bus-type: |
| 99 | + const: 4 |
| 100 | + |
| 101 | + remote-endpoint: true |
| 102 | + |
| 103 | + required: |
| 104 | + - port@0 |
| 105 | + - port@1 |
| 106 | + |
| 107 | +additionalProperties: false |
| 108 | + |
| 109 | +required: |
| 110 | + - compatible |
| 111 | + - ports |
| 112 | + |
| 113 | +examples: |
| 114 | + - | |
| 115 | + csi2: csi2@3000 { |
| 116 | + compatible = "snps,dw-csi"; |
| 117 | + reg = <0x03000 0x7FF>; |
| 118 | + phys = <&mipi_dphy_rx>; |
| 119 | + phy-names = "dphy"; |
| 120 | + resets = <&dw_rst 1>; |
| 121 | + interrupts = <2>; |
| 122 | +
|
| 123 | + ports { |
| 124 | + #address-cells = <1>; |
| 125 | + #size-cells = <0>; |
| 126 | +
|
| 127 | + port@0 { |
| 128 | + reg = <0>; |
| 129 | +
|
| 130 | + csi_ep1: endpoint { |
| 131 | + bus-type = <4>; /* MIPI CSI2 D-PHY */ |
| 132 | + remote-endpoint = <&camera_1>; |
| 133 | + data-lanes = <1 2>; |
| 134 | + clock-lanes = <0>; |
| 135 | + }; |
| 136 | + }; |
| 137 | +
|
| 138 | + port@1 { |
| 139 | + reg = <1>; |
| 140 | +
|
| 141 | + csi_ep2: endpoint { |
| 142 | + remote-endpoint = <&idi_receiver>; |
| 143 | + bus-type = <4>; |
| 144 | + }; |
| 145 | + }; |
| 146 | + }; |
| 147 | + }; |
| 148 | +
|
| 149 | +... |
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