@@ -142,6 +142,8 @@ struct at91_adc_reg_layout {
142142#define AT91_SAMA5D2_EMR_OSR_1SAMPLES 0
143143#define AT91_SAMA5D2_EMR_OSR_4SAMPLES 1
144144#define AT91_SAMA5D2_EMR_OSR_16SAMPLES 2
145+ #define AT91_SAMA5D2_EMR_OSR_64SAMPLES 3
146+ #define AT91_SAMA5D2_EMR_OSR_256SAMPLES 4
145147
146148/* Extended Mode Register - Averaging on single trigger event */
147149#define AT91_SAMA5D2_EMR_ASTE (V ) ((V) << 20)
@@ -308,6 +310,8 @@ static const struct at91_adc_reg_layout sama7g5_layout = {
308310#define AT91_OSR_1SAMPLES 1
309311#define AT91_OSR_4SAMPLES 4
310312#define AT91_OSR_16SAMPLES 16
313+ #define AT91_OSR_64SAMPLES 64
314+ #define AT91_OSR_256SAMPLES 256
311315
312316#define AT91_SAMA5D2_CHAN_SINGLE (index , num , addr ) \
313317 { \
@@ -640,7 +644,9 @@ static const struct at91_adc_platform sama7g5_platform = {
640644 .osr_mask = GENMASK (18 , 16 ),
641645 .osr_vals = BIT (AT91_SAMA5D2_EMR_OSR_1SAMPLES ) |
642646 BIT (AT91_SAMA5D2_EMR_OSR_4SAMPLES ) |
643- BIT (AT91_SAMA5D2_EMR_OSR_16SAMPLES ),
647+ BIT (AT91_SAMA5D2_EMR_OSR_16SAMPLES ) |
648+ BIT (AT91_SAMA5D2_EMR_OSR_64SAMPLES ) |
649+ BIT (AT91_SAMA5D2_EMR_OSR_256SAMPLES ),
644650 .chan_realbits = 16 ,
645651};
646652
@@ -774,6 +780,18 @@ static int at91_adc_config_emr(struct at91_adc_state *st,
774780 emr |= AT91_SAMA5D2_EMR_OSR (AT91_SAMA5D2_EMR_OSR_16SAMPLES ,
775781 osr_mask );
776782 break ;
783+ case AT91_OSR_64SAMPLES :
784+ if (!(osr_vals & BIT (AT91_SAMA5D2_EMR_OSR_64SAMPLES )))
785+ return - EINVAL ;
786+ emr |= AT91_SAMA5D2_EMR_OSR (AT91_SAMA5D2_EMR_OSR_64SAMPLES ,
787+ osr_mask );
788+ break ;
789+ case AT91_OSR_256SAMPLES :
790+ if (!(osr_vals & BIT (AT91_SAMA5D2_EMR_OSR_256SAMPLES )))
791+ return - EINVAL ;
792+ emr |= AT91_SAMA5D2_EMR_OSR (AT91_SAMA5D2_EMR_OSR_256SAMPLES ,
793+ osr_mask );
794+ break ;
777795 }
778796
779797 at91_adc_writel (st , EMR , emr );
@@ -791,6 +809,10 @@ static int at91_adc_adjust_val_osr(struct at91_adc_state *st, int *val)
791809 nbits = 13 ;
792810 else if (st -> oversampling_ratio == AT91_OSR_16SAMPLES )
793811 nbits = 14 ;
812+ else if (st -> oversampling_ratio == AT91_OSR_64SAMPLES )
813+ nbits = 15 ;
814+ else if (st -> oversampling_ratio == AT91_OSR_256SAMPLES )
815+ nbits = 16 ;
794816
795817 /*
796818 * We have nbits of real data and channel is registered as
@@ -1670,7 +1692,8 @@ static int at91_adc_write_raw(struct iio_dev *indio_dev,
16701692 switch (mask ) {
16711693 case IIO_CHAN_INFO_OVERSAMPLING_RATIO :
16721694 if ((val != AT91_OSR_1SAMPLES ) && (val != AT91_OSR_4SAMPLES ) &&
1673- (val != AT91_OSR_16SAMPLES ))
1695+ (val != AT91_OSR_16SAMPLES ) && (val != AT91_OSR_64SAMPLES ) &&
1696+ (val != AT91_OSR_256SAMPLES ))
16741697 return - EINVAL ;
16751698 /* if no change, optimize out */
16761699 if (val == st -> oversampling_ratio )
@@ -1883,7 +1906,9 @@ static IIO_CONST_ATTR(hwfifo_watermark_max, AT91_HWFIFO_MAX_SIZE_STR);
18831906static IIO_CONST_ATTR (oversampling_ratio_available ,
18841907 __stringify (AT91_OSR_1SAMPLES ) " "
18851908 __stringify (AT91_OSR_4SAMPLES ) " "
1886- __stringify (AT91_OSR_16SAMPLES )) ;
1909+ __stringify (AT91_OSR_16SAMPLES ) " "
1910+ __stringify (AT91_OSR_64SAMPLES ) " "
1911+ __stringify (AT91_OSR_256SAMPLES )) ;
18871912
18881913static struct attribute * at91_adc_attributes [] = {
18891914 & iio_const_attr_oversampling_ratio_available .dev_attr .attr ,
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