drm: atmel-hlcdc: disable clock divider to match LCDC_PCK with the src clk

When utilizing the LVDS interface, enable the ATMEL_XLCDC_CLKBYP bit in
LCDC_CFG0 for XLCDC. This configuration ensures that the LCDC pixel clock
aligns with the source clock (LVDS PLL).

Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com>

Author: Dharma Balasubiramani

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

@@ -109,39 +109,44 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c)
 		     (adj->crtc_hdisplay - 1) |
 		     ((adj->crtc_vdisplay - 1) << 16));
 
-	prate = clk_get_rate(crtc->dc->hlcdc->sys_clk);
-	mode_rate = adj->crtc_clock * 1000;
-	if (!crtc->dc->desc->fixed_clksrc) {
-		prate *= 2;
-		cfg |= ATMEL_HLCDC_CLKSEL;
-		mask |= ATMEL_HLCDC_CLKSEL;
-	}
+	if (crtc->dc->hlcdc->lvds_pll_clk) {
+		cfg |= ATMEL_XLCDC_CLKBYP;
+		mask |= ATMEL_XLCDC_CLKBYP;
+	} else {
+		prate = clk_get_rate(crtc->dc->hlcdc->sys_clk);
+		mode_rate = adj->crtc_clock * 1000;
+		if (!crtc->dc->desc->fixed_clksrc) {
+			prate *= 2;
+			cfg |= ATMEL_HLCDC_CLKSEL;
+			mask |= ATMEL_HLCDC_CLKSEL;
+		}
 
-	div = DIV_ROUND_UP(prate, mode_rate);
-	if (div < 2) {
-		div = 2;
-	} else if (ATMEL_HLCDC_CLKDIV(div) & ~ATMEL_HLCDC_CLKDIV_MASK) {
-		/* The divider ended up too big, try a lower base rate. */
-		cfg &= ~ATMEL_HLCDC_CLKSEL;
-		prate /= 2;
 		div = DIV_ROUND_UP(prate, mode_rate);
-		if (ATMEL_HLCDC_CLKDIV(div) & ~ATMEL_HLCDC_CLKDIV_MASK)
-			div = ATMEL_HLCDC_CLKDIV_MASK;
-	} else {
-		int div_low = prate / mode_rate;
+		if (div < 2) {
+			div = 2;
+		} else if (ATMEL_HLCDC_CLKDIV(div) & ~ATMEL_HLCDC_CLKDIV_MASK) {
+			/* The divider ended up too big, try a lower base rate. */
+			cfg &= ~ATMEL_HLCDC_CLKSEL;
+			prate /= 2;
+			div = DIV_ROUND_UP(prate, mode_rate);
+			if (ATMEL_HLCDC_CLKDIV(div) & ~ATMEL_HLCDC_CLKDIV_MASK)
+				div = ATMEL_HLCDC_CLKDIV_MASK;
+		} else {
+			int div_low = prate / mode_rate;
 
-		if (div_low >= 2 &&
-		    (10 * (prate / div_low - mode_rate) <
-		     (mode_rate - prate / div)))
 			/*
-			 * At least 10 times better when using a higher
+			 * Its better to use a higher Pixel clock
 			 * frequency than requested, instead of a lower.
 			 * So, go with that.
 			 */
-			div = div_low;
-	}
 
-	cfg |= ATMEL_HLCDC_CLKDIV(div);
+			if (div_low >= 2 &&
+			    ((prate / div_low >= mode_rate) &&
+			     (prate / div < mode_rate)))
+				div = div_low;
+		}
+		cfg |= ATMEL_HLCDC_CLKDIV(div);
+	}
 
 	regmap_update_bits(regmap, ATMEL_HLCDC_CFG(0), mask, cfg);
 

include/linux/mfd/atmel-hlcdc.h

@@ -44,6 +44,7 @@
 #define ATMEL_XLCDC_HEO_UPDATE		BIT(3)
 
 #define ATMEL_HLCDC_CLKPOL		BIT(0)
+#define ATMEL_XLCDC_CLKBYP		BIT(1)
 #define ATMEL_HLCDC_CLKSEL		BIT(2)
 #define ATMEL_HLCDC_CLKPWMSEL		BIT(3)
 #define ATMEL_HLCDC_CGDIS(i)		BIT(8 + (i))