mfd: atmel-hlcdc: set prepare and enable LVDS PLL clock for LVDS display

The XLCDC IP in sam9x7 supports DSI, parallel RGB and LVDS Display.
sys_clk (Generic clock) of atmel-hlcdc is used with DSI and Parallel
RGB and LVDS PLL is used with LVDS display.

Set the LVDS PLL clock rate by querying the panel's pixel clock frequency.

prepare and enable the lvds_pll_clk, if it is configured in DT.

Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com>
[manikandan.m@microchip.com: ported to v6.6.9 by fixing conflicts in
clock prepare/enable of lvds_pll_clk]
Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>

Author: Dharma Balasubiramani

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

@@ -100,9 +100,15 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c)
 		drm_connector_list_iter_end(&iter);
 	}
 
-	ret = clk_prepare_enable(crtc->dc->hlcdc->sys_clk);
-	if (ret)
-		return;
+	if (crtc->dc->hlcdc->lvds_pll_clk) {
+		ret = clk_prepare_enable(crtc->dc->hlcdc->lvds_pll_clk);
+		if (ret)
+			return;
+	} else {
+		ret = clk_prepare_enable(crtc->dc->hlcdc->sys_clk);
+		if (ret)
+			return;
+	}
 
 	vm.vfront_porch = adj->crtc_vsync_start - adj->crtc_vdisplay;
 	vm.vback_porch = adj->crtc_vtotal - adj->crtc_vsync_end;
@@ -185,7 +191,10 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c)
 			   ATMEL_XLCDC_DPI : ATMEL_HLCDC_MODE_MASK),
 			   cfg);
 
-	clk_disable_unprepare(crtc->dc->hlcdc->sys_clk);
+	if (crtc->dc->hlcdc->lvds_pll_clk)
+		clk_disable_unprepare(crtc->dc->hlcdc->lvds_pll_clk);
+	else
+		clk_disable_unprepare(crtc->dc->hlcdc->sys_clk);
 }
 
 static enum drm_mode_status
@@ -238,7 +247,11 @@ static void atmel_hlcdc_crtc_atomic_disable(struct drm_crtc *c,
 	       (status & ATMEL_HLCDC_PIXEL_CLK))
 		cpu_relax();
 
-	clk_disable_unprepare(crtc->dc->hlcdc->sys_clk);
+	if (crtc->dc->hlcdc->lvds_pll_clk)
+		clk_disable_unprepare(crtc->dc->hlcdc->lvds_pll_clk);
+	else
+		clk_disable_unprepare(crtc->dc->hlcdc->sys_clk);
+
 	pinctrl_pm_select_sleep_state(dev->dev);
 
 	pm_runtime_allow(dev->dev);
@@ -251,15 +264,37 @@ static void atmel_hlcdc_crtc_atomic_enable(struct drm_crtc *c,
 {
 	struct drm_device *dev = c->dev;
 	struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
+	struct drm_display_mode *adj = &c->state->adjusted_mode;
 	struct regmap *regmap = crtc->dc->hlcdc->regmap;
 	unsigned int status;
+	int ret;
 
 	pm_runtime_get_sync(dev->dev);
 
 	pm_runtime_forbid(dev->dev);
 
 	pinctrl_pm_select_default_state(dev->dev);
-	clk_prepare_enable(crtc->dc->hlcdc->sys_clk);
+
+	if (crtc->dc->hlcdc->lvds_pll_clk) {
+		/* If the LVDS interface is used, fetch the pixel clock
+		 * from the panel and set the clock rate.
+		 * Here LVDS PLL clock is 7 times the pixel clock.
+		 */
+		ret = clk_set_rate(crtc->dc->hlcdc->lvds_pll_clk,
+				   (adj->clock * 7 * 1000));
+		if (ret) {
+			dev_err(c->dev->dev, "failed to set clk rate for lvds pll: %d\n", ret);
+			return;
+		}
+
+		ret = clk_prepare_enable(crtc->dc->hlcdc->lvds_pll_clk);
+		if (ret)
+			return;
+	} else {
+		ret = clk_prepare_enable(crtc->dc->hlcdc->sys_clk);
+		if (ret)
+			return;
+	}
 
 	regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_PIXEL_CLK);
 	while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&

drivers/mfd/atmel-hlcdc.c

@@ -114,6 +114,13 @@ static int atmel_hlcdc_probe(struct platform_device *pdev)
 		return PTR_ERR(hlcdc->sys_clk);
 	}
 
+	/* Get the optional clock (LVDS PLL) in case if the LVDS interface is used */
+	hlcdc->lvds_pll_clk = devm_clk_get_optional(dev, "lvds_pll_clk");
+	if (IS_ERR(hlcdc->lvds_pll_clk)) {
+		dev_info(dev, "failed to get lvds PLL clock\n");
+		hlcdc->lvds_pll_clk = NULL;
+	}
+
 	hlcdc->slow_clk = devm_clk_get(dev, "slow_clk");
 	if (IS_ERR(hlcdc->slow_clk)) {
 		dev_err(dev, "failed to get slow clock\n");

include/linux/mfd/atmel-hlcdc.h

@@ -75,6 +75,7 @@
  */
 struct atmel_hlcdc {
 	struct regmap *regmap;
+	struct clk *lvds_pll_clk;
 	struct clk *periph_clk;
 	struct clk *sys_clk;
 	struct clk *slow_clk;